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PVS LVS reporting missing pins in Layout

Waleed Mansha

I have done the layout of a cell and included all the pins that were in the schematic by using "generate selected from source" for each one of them and choosing the appropriate pin layer. The "connectivity -> check --> against source"  and "connectivity--> update --> components and nets" validates that the pins have bee placed.

DRC with PVS is clean.

Running LVS with PVS results in mismatch showing all pins are missing in layout.

  • Saloni Chhabra

    Can you try setting 'Convert Pin' option under 'Input' section of PVS LS form as shown below (and then re-run LVS):

  • Waleed Mansha
    in reply to Saloni Chhabra

    I have tried that but LVS still doesn't recognize any pins.
    My pins are on metal layer with purpose"pin". Their labels are on the same metal layer with purpose "label". I have tried placing the labels on the drawing layer as well but still no luck. 

  • Quek
    in reply to Waleed Mansha

    Hi Waleed

    Perhaps you can try this:

    a. Execute the following cmd in a terminal window:
    terminal> egrep "port -text_layer" /your-path/PVS_LVS.rul

    You may get something similar to this:
    port -text_layer m1_pin

    b. Now execute this:
    terminal> egrep "layer_def m1_pin" /your-path/PVS_LVS.rul

    Output may be similar to this:
    layer_def m1_pin 1087

    c. Now execute this:
    terminal> egrep "layer_map.*1087" /your-path/PVS_LVS.rul

    Output may be similar to this:
    layer_map 7 -texttype 1 1087

    You now need to know the DFII layer name and purpose of gds number 7 type 1. You can check Virtuoso gds mapping file for the info. E.g.

    Metal1 pin 7 1

    Now we know that you need to use "pin" purpose for the label. : )


    Best regards
    Quek

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