Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in verilog A when they are used in 'if -else statement'

They're not identical - because the first is like having a zero-volt source between the two nets, and the second is like a voltage-controlled voltage source. So that means that in the first case current flows between P1 and T1, but it doesn't in the second case.

You should never (well, almost never) put contribution statements within an if statement (the "almost" case is when you have a switch branch which switches from a voltage source to a current source - usually to model a switch opening or closing). Otherwise you end up with a contribution that isn't active all the time, and the node (or branch) ends up uncontrolled for some of the time, which presents a problem for the matrix solver, as it means you have an ill-conditioned matrix to solve.

Regards,

Andrew.

thank you for your explanation. I am trying to simulate a switch and when I used these statements in an 'if block', I get 'zero diagonal and jacobian' errors. Could you please suggest the best choice if I am simulating an switch

If you want an explanation as to why your model misbehaves, it's generally best to actually show your model. My extra-sensory-veriloga-perception isn't working too well at the moment (I blame jet lag), so I can't guess what you've done.

For some examples of switch models, see http://www.designers-guide.org/VerilogAMS/ 

Regards,

Andrew.

If you want to learn how to best model a switch (and why), I would suggest you to take a look at chapter 3 of the Mixed-Signal Methodology Guide, which is available at https://www.eetimes.com/author.asp?section_id=36&doc_id=1286611 (especially the section "Example of Modeling with Proper Continuity" in part 4).

Andrew, my apologies, I should have given the model here. I have already seen the switch models in 'Designer's guide'. Here is my code:

`include "constants.vams"
`include "disciplines.vams"

module MIMO_DPNT(P1,P2,T1,T2,T3,Tgnd,Tgnd2,VG11,VG12,VG13,VG28,VG1_Term,VG1_Iso,VG2_Term,VG2_Iso);
input VG11,VG12,VG13,VG28,VG1_Term,VG1_Iso,VG2_Term,VG2_Iso;
inout P1,P2,T1,T2,T3,T8,Tgnd,Tgnd2;
electrical P1,P2,T1,T2,T3,T8,Tgnd,Tgnd2,VG11,VG12,VG13,VG28,VG1_Term,VG1_Iso,VG2_Term,VG2_Iso;

analog begin
     //Specify single port connections for Port1 & Port2
     if(V(VG28) < 0.1) begin
            if(V(VG11)>0.1) 
                 V(P1) <+ V(T1);
            else
                  I(P1,T1) <+ 1e-8;

             if(V(VG12)>0.1) 
                 V(P1) <+ V(T2);
             else
                  I(P1,T2) <+ 1e-8;

              if(V(VG13)>0.1) 
                   V(P1,T3) <+ 0;
              else
                   I(P1,T3) <+ 1e-8;
              I(P2,T8) <+ 1e-8;
      end
      else
      V(P2,T8) <+ 0;

      if (V(VG2_Iso) > 0.1)
            V(P2,Tgnd2) <+ 0;
      else if (V(VG2_Term) > 0.1)
             I(P2,Tgnd2) <+ V(P2,Tgnd2)/50;
      else
             I(P2,Tgnd2) <+ 1e-8;

       if (V(VG1_Iso)>0.1)
             V(P1,Tgnd) <+ 0;
       else if (V(VG1_Term)>0.1)
              I(P1,Tgnd) <+ V(P1,Tgnd)/50;
       else
               I(P1,Tgnd) <+ 1e-8;

end
endmodule

The error I am getting is "Zero diagonal found in Jacobian at xxxxx node" and the DC convergence is not happening due to this block, can you please let me know where I went wrong?

Thank you Frank, I will look into the book that you have suggested

If it's not happening due to this block, I'm not sure how you expect me to debug it?

Anyway, the only valid use of a "switch" branch is when you have the same branch between the then and else part, where you change from (say) a voltage source to a current source on the same branch. In cases like this:

            if(V(VG11)>0.1) 
                 V(P1) <+ V(T1);
            else
                  I(P1,T1) <+ 1e-8;

they are not the same branch, for the reasons I stated above.  You're changing from a voltage controlled source to a small leakage current between the two.

Andrew.

If it's not happening due to this block, I'm not sure how you expect me to debug it?

Anyway, the only valid use of a "switch" branch is when you have the same branch between the then and else part, where you change from (say) a voltage source to a current source on the same branch. In cases like this:

            if(V(VG11)>0.1) 
                 V(P1) <+ V(T1);
            else
                  I(P1,T1) <+ 1e-8;

they are not the same branch, for the reasons I stated above.  You're changing from a voltage controlled source to a small leakage current between the two.

Andrew.

I understand what you were saying, I have in fact given the following code initially:

            if(V(VG11)>0.1) 
                 V(P1,T1)  <+ 0;
            else
                  I(P1,T1) <+ 1e-8;

Is this the right way of defining a connection for a switch? 

Yes, although you may need to take care of the fact that this is discontinuous - probably the link that Frank pointed to covers how to better handle that (I didn't check). The examples on the Designer's Guide that I mentioned are similar (these are from the book by Ken Kundert and Olaf Zinke - The Designer's Guide to Verilog AMS).

Andrew.

Andrew, thank you for the information, can you be elaborate more on how it is discontinuous?

Quite simply, the switch changes position instantaneously - and so the impedance of the switch changes instantaneously. That means there would be a discontinuity in the current through the switch or the voltage across the switch. In the models on the Designer's Guide site, it does at least announce the discontinuity, and that's better than nothing. Circuit simulators don't really like ideal behaviour like this, and a model will work better if it is more realistic about modelling the transition. I'm sure this is covered in Ken and Olaf's book (I don't have a copy with me today so can't give you a reference), and is certainly covered in the Mixed-Signal Methodology Guide that Frank mentioned earlier - it's in the section Analog Best Practices from page 55 onwards.

Regards,

Andrew.