Create a symbol from layout

This is a bit of an open-ended question, especially as you didn't say which tools you're using. Which LVS tool are you using? I wouldn't expect that you'd get an error saying that a symbol couldn't be read though. Broadly speaking I'd expect that you have to:

1. Create the symbol with the right pins
2. Copy this across to the auCdl view (or auLvs view - depends on which tool you're using for LVS)
3. In the CDF, ensure that the component will be netlisted correctly to match your LVS extraction rules
4. In the LVS deck, you'll have to add logic to recognise the device - i.e. some kind of recognition layer to identify the device correctly and figure out the connectivity to the pins. Maybe some parameter extraction to work out whether the dimensions of the transformer match the schematic, if you're not going to treat it as a black box.

Alternatively, you might just create a schematic for the transformer with metal resistors at each pin to stop the pins from being seen as shorts (since the transformer coils are just metal tracks between pins), and then add those metal resistors on the transformer layout. It's not really checking that the transformer is present in the LVS, but at least you can manually check the transformer and allow a component in the schematic for simulation without it getting in the way of LVS.

If this is unclear, contacting customer support would be a good idea. Trying to explain all this (briefly) in a public forum with such little information to go on is quite hard!

Regards,

Andrew.

Hi

Thank you for your attention

I am using Keysight Momentum-Virtuoso tool (Momentum for golden gate tools) for creation of symbol

for LVS tool i am using Calibre tool and nmLVS.

1. I have created the symbol with right pins configuration, actually the symbol has been created by a tool that is for creation of circuit simulator view from Keysight Momentum-Virtuoso

2. I have crated auCdl view from Symbol due to using Calibre tool for Lvs

but I have got the following error

*Error* Cell: MN_V1_23_07  in library: mahanisi is

missing a simInfo section in it's CDF for the current

simulator

Dear Andrew could you please guide me, how could i complete the CDF for the mentioned error?

I can't help you with Calibre (it's a Mentor tool) or Momentum or Golden Gate (they're Keysight tools), but if you know what the CDL needs to look like, it should just be a matter of defining in the Tools->CDF->Edit in the CIW, picking "Base" and then lib/cell for the component, and then in the Simulation Information tab, pick "auCdl" from the cyclic field, and fill in a netlist procedure (probably pick something like ansCdlCompPrim), and then the termOrder being the names of the pins of your component - you may need to be careful about the order, I don't know. The modelName should be whatever Calibre will use to recognise the device.

For the most part, you probably would be best to ask Mentor about this, because the main challenge will be getting Calibre to recognise the device. Once that's sorted out, I'm sure they can help you get the netlisting sorted out so that it netlists whatever Calibre LVS is expecting.

Regards,

Andrew.

Ok

Thank you for your attention

Sincerely

Hi Dear Andrew

Due to my problem for checking LVS:

I am trying to make a netlist by Virtuoso CDL Out from my schematic that includes the symbol which i have created.

I have attached the CDL out template, also the output netlist file and the source.added file are in the following respectively:

************************************************************************
* auCdl Netlist:
*
* Library Name:  mahanisi
* Top Cell Name: TB_LVS
* View Name:     schematic
* Netlisted on:  Aug  2 09:28:40 2018
************************************************************************

.INCLUDE  /.../source.added
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: mahanisi
* Cell Name:    TB_LVS
* View Name:    schematic
************************************************************************
.SUBCKT TB_LVS pNEG pPOS pS_NEG pS_POS
*.PININFO pNEG:B pPOS:B pS_NEG:B pS_POS:B
XC0 pS_POS pS_NEG pS_NEG crtmom_rf nv=288 nh=288 w=160.0n s=160.0n stm=3 spm=5
+ m=1
XI13 pNEG pPOS pS_NEG pS_POS

.ENDS

source.added file's text is in the following:

* SPICE NETLIST
***************************************

.SUBCKT MN_V1_23_07_can NEG  POS  S_NEG  S_POS  
.ENDS

***************************************

Could you please take a look at them and investigate my problem?

The problem is:

When the netlist is created by CDL Out the subcircuit can not be detected, however i have added the intended subcircuit in source.added file by myself.

Hi Dear Andrew

Due to my problem for checking LVS:

I am trying to make a netlist by Virtuoso CDL Out from my schematic that includes the symbol which i have created.

I have attached the CDL out template, also the output netlist file and the source.added file are in the following respectively:

************************************************************************
* auCdl Netlist:
*
* Library Name:  mahanisi
* Top Cell Name: TB_LVS
* View Name:     schematic
* Netlisted on:  Aug  2 09:28:40 2018
************************************************************************

.INCLUDE  /.../source.added
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: mahanisi
* Cell Name:    TB_LVS
* View Name:    schematic
************************************************************************
.SUBCKT TB_LVS pNEG pPOS pS_NEG pS_POS
*.PININFO pNEG:B pPOS:B pS_NEG:B pS_POS:B
XC0 pS_POS pS_NEG pS_NEG crtmom_rf nv=288 nh=288 w=160.0n s=160.0n stm=3 spm=5
+ m=1
XI13 pNEG pPOS pS_NEG pS_POS

.ENDS

source.added file's text is in the following:

* SPICE NETLIST
***************************************

.SUBCKT MN_V1_23_07_can NEG  POS  S_NEG  S_POS  
.ENDS

***************************************

Could you please take a look at them and investigate my problem?

The problem is:

When the netlist is created by CDL Out the subcircuit can not be detected, however i have added the intended subcircuit in source.added file by myself.