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Strange problem when working with small currents in ADE L

dpalomeq

Hi,

I noticed a problem when simulating in ADE L with a 0.18um technology. For a simple current mirror, I found that results are not reliable for small currents (in the order of nA) if transistors’ parameters W and L are directly set. On the contrary, if the multiplier parameter is used, simulation results match with those expected. Moreover, for currents in the order of μA, simulation results are always as expected.

The schematic is this one:

Results of 10 DC operating point simulations are shown in these Tables. As you can guess by noticing the VDS,sat value, the level of inversion is kept more or less constant across simulations. For small current, only setting the multiplier parameter works. On the contrary, for higher currents, either using multiplier of directly setting the values of transistors work as expected. It is also worth noting that scaling the Lenght of the transistor instead of the Width WORKS both for small and high currents.

 

Sim 1

Sim 2

Sim 3

Sim 4

Sim 5

V0 [V]

1.8

1.8

1.8

1.8

1.8

I0 [nA]

5

5

5

5

5

R0 [MΩ]

20

20

20

20

20

W0 [μm]

0.5

0.5

0.5

0.5

0.5

L0 [μm]

0.5

0.5

0.5

0.5

0.5

W1 [μm]

0.5

1

2

0.5

0.5

L1 [μm]

0.5

0.5

0.5

0.5

0.5

multiplier1

1

1

1

2

4

VX1 [mV]

270.208

270.208

270.208

270.208

270.208

VX2 [V]

1.678

1.6722

1.593

1.558

1.328

VDS,sat1 [mV]

43.381

43.381

43.381

43.381

43.381

VDS,sat2 [mV]

43.381

43.223

44.632

43.381

43.381

Iout [nA]

6.11

6.39

10.33

12.08

23.58

 

Sim 6

Sim 7

Sim 8

Sim 9

Sim 10

V0 [V]

1.8

1.8

1.8

1.8

1.8

I0 [μA]

1

1

1

1

1

R0 [kΩ]

100

100

100

100

100

W0 [μm]

100

100

100

100

100

L0 [μm]

0.5

0.5

0.5

0.5

0.5

W1 [μm]

100

200

400

100

100

L1 [μm]

0.5

0.5

0.5

0.5

0.5

multiplier1

1

1

1

2

4

VX1 [mV]

306.559

306.559

306.559

306.559

306.559

VX2 [V]

1.682

1.567

1.344

1.567

1.342

VDS,sat1 [mV]

46.845

46.845

46.845

46.845

46.845

VDS,sat2 [mV]

46.845

46.842

46.841

46.845

46.845

Iout [μA]

1.18

2.33

4.55

2.34

4.56

What could be happeining here?

Thanks in advanced!

  • Andrew Beckett

    If I've understood what you're trying to do correctly here, then you are mistaken in your belief that doubling W is the same as doubling the multiplier. It isn't. The effective width of the transistor has some "delta W" effects that are constant and so the effective width is typically a little different the the  width you enter (this can be modelling effects such as offsets in the mask, or etching effects, amongst others). For example, in the bsim4 chapter of the Spectre Circuit Simulator Components and Device Models Reference manual, there is a section Effective Oxide Thickness, Channel Length and Channel Width. This shows this equation:

    So this means there's a fixed offset, unrelated to the width, and so the effective width does not double when you double the width of the transistor. That effect is much smaller when the width is larger in the first place, which is what your second row shows. Specifying m however is the same as having two transistors in parallel, and so in that case both the width and delta-width are applied in parallel and so it does scale as you're expecting.

    Regards,

    Andrew.

  • dpalomeq
    in reply to Andrew Beckett

    Hello Andrew,

    Thanks for your detailed response. There is only one thing I see in simluations I can not fit with your response. If I force a 5 nA current to flow through a 0.5/0.5 transistor and I try to double the current with a 0.5/0.25 transistor, the copy is perfectly done. From the document you mention I see that (obviously) there is also a difference between the effective L and the drawn L accounting for different effects that occur in the fabrication process. Shouldn't be this copy also heavily affected?

    Regards,

    David.

  • Andrew Beckett
    in reply to dpalomeq

    David,

    It's possible that the delta-L is 0 in the models, and so they scale OK when the length is halved (I can't know without seeing the models - I'm not asking you to post them here because that would almost certainly break an NDA).

    Regardless of this, no analog IC designer would (or rather should) implement scaling in a current mirror by having a device with a multiple of the width or length. You should always use unit devices and have a number of them in parallel (this is what m factor does) - that way the devices can be matched.

    Regards,

    Andrew.

  • dpalomeq
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks again for your response. You are right, I can't post the models. In addition, I tested this in another different 0.18 um technology and it doesn't happen.

    Of course, I am not designing anything by multiplying the width. I posted this testbench because it showed clearly the problem I was having and I could not explaining (I was starting to think that I was missing some important basic aspect of analog CMOS design). I will check the value delta-L is adopting, just willing to clarify this.

    Regards,

    David.

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