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Preventing a stupid schematic mistake with NMOS back-gates

CADcasualty

I have a question that I suspect is more of a pdk thing than a Cadence thing. A regular PMOS symbol in our TSMC 0.18um library has 4 terminals (D, G. S. BG). That's fine. A regular NMOS symbol also has 4 terminals (D, G. S. BG) but that's not so fine because the BG terminal is really the substrate and there's only one place that should (normally) be connected i.e. ground. Having it available as a pin enables trouble because you can connect it to anything. Note that the library also contains isolated deep n-well NMOS devices that do have a valid BG terminal, but I'm focusing on just the regular NMOS for this discussion.

In the attached diagram, I show two NMOS "diode" stacks. The left stack has all the NMOS devices having their BG terminals connected to ground. The right stack has all the NMOS devices with their BG terminals connected to their source terminals. In the real world, the BG terminals in the bad stack would short their source terminals to ground so you'd only end up with one effective diode in that stack (the top one).

Some thoughts: when you do a check and save on the attached circuit you'd hope that you'd get an error for the bad stack (global substrate shorting out multiple different nets), but you don't. When you run a simulation of the circuit in Spectre it works just fine - no warnings or errors and the bad stack produces an accumulating set of Vgs voltages just like the good stack.

We just had a situation where a designer who should have known better used a bad stack and made a perfectly functional circuit that met all specs :-/. Is there a way to catch this at the schematic check and save time? This sort of thing shouldn't be happening in 2018...

  • I should have added that the bad NMOS diode stack (after simulation) just consists of 3 Vgs voltages that don't show any of the back-gate effect on each device's threshold voltage like the good stack does i.e. each Vgs in the bad stack is the same.

  • in reply to CADcasualty

    A custom schematic check could certainly be added to do this - obviously Cadence can't do this out of the box because it depends on the technology - we have no way of knowing whether the device has an isolated well (or even what type the substrate was) or is just indicating that you want a strong connection to the ground in metal (with substrate ties). I'm sure LVS would normally pick this up, but it's a bit late. I think you could also do it with asserts in spectre to see if the bulk node wasn't zero (obviously these asserts would needed to be included along with the models). A connectivity-based check at check-and-save time would certainly be feasible though.

    There's several places I've posted example schematic check code - e.g. in this post. It would be easy enough to code a check that looked at the bulk pins of a set of devices and checked that they were connected to a reasonable node in the design.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Thanks for the advice and also the link to your code. I'll see what we can be tweaked for this case. I attribute this issue to the pdk not being well thought out, which is kind of poor given that it's a very mature process...

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