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verilog-a model help

SatendraMaurya

Hi,

I am new to verilogA. I am looking for veriloga code that generates a text output whenever gate of any transistor pmos or nmos rises to a file.

Satendra

  • Andrew Beckett
    in reply to SatendraMaurya
    SatendraMaurya said:
    Will talk to the pdk guys about the terminal naming?

    Was that intended to be a question? It's not clear to me what the terminal naming has to do with anything here...

    Andrew.

  • SatendraMaurya
    in reply to Andrew Beckett

    No its not a question to Cadence but to the foundry pdk people to how to annotate the fet terminals. At one time we use to have M1.n1(for drain) M1.n2(for gate) and so forth. Another time we had M1.D/M1.G etc. I tried all of these but none worked. But I have a feeling that there is a way to get to that.

    Satendra

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