verilog-a model help

Hi Satendra,

 You can use the $fstrobe, $fdisplay, $fwrite function to write to a file. You'll need to use the $fopen function first to create the file. For more details look at the 'Writing to a File' section in module 9 in the 'Cadence Verilog-A Language Reference'. There is also a simple example there. I'm posting the link from the support site below:

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=veriaref.xml&title=Cadence%20Verilog-A%20Language%20Reference%20--%209%20-%20Writing%20to%20a%20File&hash=1038148&c_version=18.1&sq=005d0000002mxbiAAA_2018823143047383&path=veriaref/veriaref18.1/chap9.html#1038148

Regards,

Dimitra

Hi Dimitra,

How to get the gate voltage for a transistor. In spice v2(xi0.xi2.xileft.mn6) works but veriloga does not understand v2. So how can I get the gate voltage of a transistor in the hierarchy.

Satendra

Your question is rather open-ended and lacking in context. I'm guessing you want to use the $cds_get_analog_value (which can be abbreviated to $cgav). See the documentation for more details.

Andrew.

Hi Andrew,

I have this in the veriloga code

@(cross(V(sig)-(ref_vdd/2), +1)) begin
$fstrobe(fptr, "%s: at t = %E s.\n",signal_name, $abstime );
end

where sig is passed as: I0.IBANK\<3\>.ICTRL.I12.MNA1

which is a transistor instance. Now the function should evaluate based on the voltage of this transistor. In hspice v2(I0.IBANK\<3\>.ICTRL.I12.MNA1) gives the gate voltage but verilogA only has v(sig).

Not sure how to use $cgav to get this done.

Satendra

Hi Satendra,

Which simulator are you using, by the way? You refer to HSPICE, so if you are, the $cgav function is probably not going to help you anyway. If using spectre, you'd give the hierarchical path to the node connected to the gate of the transistor, rather than just the name of the transistor itself and having a function look at the voltage on the second pin.

Regards,

Andrew.

Just as a note, the @(cross()) event is important because it will influence the simulator timestep near the crossing but the value you get for $abstime will be slightly past the actual crossing.  It is better to last_crossing() to get the actual (well, interpolated) crossing time (but keep the @(cross()) event which helps the simulator know that you have an interest in an event near there and helps with timestep control.

Hi Andrew,

I am using Spectre so the node name works. I am able to probe. Just wondering there is not way to get the trasistor gate node name in verilogA. Reason being we may switch simulator later and then will have to rework this all over again. I am surprised how is v2() able to give me info. Is there a way to debug the code that runs v2(). I am sure v2() is calling v() along with some more param that enable it to measure the gate voltage.

Satendra

Hi drdanmc,

I am confused. You suggested to use both cross() and last_cross(). But I only have one usage in my code. Do you mind correcting the code and send it back.

Satendra

There is no equivalent of v2() in VerilogA (regardless of the simulator). The v2() you are thinking of is an HSPICE netlist construct. You can do the same thing in Spectre using (for example):

simulator lang=spice
.probe v2(MP1)

However, as I said, there's no v2 in the VerilogA language. You are mixing up the V() access function in VerilogA with the V function in the SPICE netlist language - they are not the same thing.

Regards,

Andrew.

Thanks for the clarification Andrew. Will talk to the pdk guys about the terminal naming?

Satendra