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Passing a string as a design variable in ADEXL

apskohli

Hello All,

I have a simulation setup where I'm writing output to a file, for post-processing; the file is created using a Verilog-A module and I have parameterized the

file name, and this all works fine in ADEL. However, when I try to run a corner sweep in ADEXL, I want to pass the output filename thru the corner setup,

in this case the input.scs contains "netlist" as an include, and the method fails.

Is there a way in ADEXL to avoid to creating a hierarchical netlist, and instead have the flat netlist as created in ADEL, i.e. not .include the netlist? or a better work around.

I would really appreciate your inputs on this issue.

Thanks,

AS

  • Andrew Beckett

    I don't see why having the "netlist" included would make any difference here. Why does that cause a problem? I don't see why that would impact the ability to make the filename a variable through corner setup - the variables are not defined in the included netlist. I also don't think what you're asking about flat versus hierarchical makes sense either - ADE L doesn't create a flat netlist - it's hierarchical just as it is in ADE XL.

    Most likely the include mechanism is as a consequence of having ignoreDesignChangesDuringRun set somewhere in your environment:

    envSetVal("adexl.simulation" "ignoreDesignChangesDuringRun" 'boolean t)

    This in turn forces this variable to t:

    envSetVal( "adexl.simulation" "includeStatementForNetlistInSimInputFile" 'boolean nil )

    (note that this variable has no effect if ignoreDesignChangesDuringRun is set to t).

    Regards,

    Andrew.

  • apskohli
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks for your reply. I guess I need to rethink my approach.

    I'm trying to save the output thru a verilog-A measurement block to a file. I need to

    do this for multiple runs of transient-noise analysis, so each file needs to be separate

    entity. Any suggestion on how to accomplish this?

    Best Regards,

    AS

  • Andrew Beckett
    in reply to apskohli
    Andrew Beckett said:
    I don't see why having the "netlist" included would make any difference here. Why does that cause a problem? I don't see why that would impact the ability to make the filename a variable through corner setup - the variables are not defined in the included netlist. I also don't think what you're asking about flat versus hierarchical makes sense either - ADE L doesn't create a flat netlist - it's hierarchical just as it is in ADE XL.

    As I said 2 months ago, I don't know what your problem actually is - this ought to work, and I didn't think then that it had any thing to do with the netlist being included the way it is in ADE XL.

    Perhaps you should contact customer support so an application engineer can look at your set up and find out what is wrong?

    Regards,

    Andrew.

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