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Pin mismatch between Symbols and Schematics

anurans

Hi All,

When generating the standard cell schematics (from .cdl) for an OA library from the scratch (in IC6), sometimes the discrepancies can be noticed between the symbol and schematic views, as in:

Warning: Terminal "RQ2B" in view schematic is (input) but is (output) in "REG2M1S symbol".

I use Import -> Spice.... to import the netlist of standard cells in .cdl format. The pin directions in the symbol seem to be correct. Is there a way to fix this issue at once for large number of cells?

Thanks in advance

Anuradha

  • Quek

    Hi Anuradha

    The CDL netlist needs to have "PININFO" lines so that the correct pin types (input, output inputOutput) can be created during spice-in. E.g.

    .SUBCKT inv1 GND IN<0> OUT VDD
    *.PININFO IN<0>:I OUT:O GND:B VDD:B

    You can use the perl script in COS article 11693840 to add pin info from the stdcell verilog file.


    Best regards
    Quek

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