failure with using amsd block

Hi Yi,

tools internally create the spice-skeleton file, you shouldn't care about it.

it is not clear by statement "Unfortunately, the end results is not good", could you please explain.

Thanks

Nasser

Hi Nasser

Thank you for replying.

The problem I am facing is that the ana_top cell seems to be empty.

When I use the "source_browser" to open the snapshot, the content of the the "ana_top" cell is just pin definition, parameter definition (it seems that the parameter is derived from the model file)

And there is no internal net /sub-blocks when I check with the "Design Browser"

But no real content for the design.

I have tried to run the simulation, it finishes super fast (run 1ms is finished within a second), even faster then the RTL simulation, which is not normal.

And no activities on the ana_top outputs.

And when I look at the log file again, I see two message for resolved instance, like:

Resolved design unit 'ana_top' at 'TB.dut@DUT<module>.acore' to spice subckt.
Resolved design unit 'ana_top' at 'TB.dut@DUT<module>.acore' to 'worklib.ana_top:spice_skeleton'.

Is this double resolving a normal behavior?

I am suspecting the binding to spice-subckt is overwritten by the second binding spice_skeleton.

Best Regards

Yi

Some follow up:

My colleague goes through the flow with me again, and comparing with her successful one:

• The amsd flow looks fine
  • port-bindings are done correctly
  • The skeleton interface is created and used in the simulation.
  • source-code of the spice-skeleton looks the same in both
  • In the simulation results, the interface and connect module around it are observed

But we have no clue, why the spice netlist is not in the simulation in the end.

Hope some one can point it out where I miss in the irun setup.

Best Regards

Yi

Hi Yi,

Your setup looks correct. Have you got any save statements in analogControl.scs, or are you providing a probe.tcl file to irun? With the correct save/probe statements, you should be able to see the content inside your analog block as well. It is possible that your analog block isn't getting the correct inputs (e.g. supplies) which is why the simulation runs fast.

Regards,

Saloni

I missed an important point. Please check your simulation log (irun.log) to see what circuit inventory says. By looking at the number of devices and nodes in the transistor-level circuit, hopefully you will get an idea whether the correct ana_top represenation has been used or not.

An example:

Circuit inventory:
              nodes 8
              bsim4 2     
     bsource_2b273e 2     
connectLib__Bidir_2__module__0x10000001_behavioral 3     

Hi Saloni

Thanks a lot, the circuit inventory is really helpful.

I see such number in the log file:

Circuit inventory:
nodes 23917
bjt 2
bsim4 11290
bsource_04fdc6 112
bsource_3166b9 208
bsource_a6a55c 170
bsource_cb93ba 16

So the spice netlist is indeed in the simulation.

Then I can focus on the debugging, might some connect module need some special setup.

I will try to add probe.tcl file to have some inside of the sub-blocks.

It's my first time to setup amsd, and dive into it.

 Best Regards

Yi