AMS simulation on a synthesized netlists --- NO sim result

Hi there!

I am trying to run ams simulation for a big design mixed of digital and analog. However, the output of simulation for the digial block is always tied to zero and basically there is no output.

Can anyone help me out  through this problem? (The following is briefly explaining the steps done)

Cadence Virtuoso: 6.1.7 -- INCISIV 15.2 (irun 15.2)

Digital part of the design is a verilog netlists generated from synthesis tool (generated netlists using both Cadence Genus and Synopsys Design-vision).

it means inside the netlists all behavioral modules have been already translated and mapped to technology components.

These steps have been all done:

1. Importing the netlists using CIW-import-verilg and a new cell generation including a verilog view
2. creating a  Config view
3. Testbench
4. ADEL and changing design to config
5. changing the view of digital block to verilog view
6. Changing the simulator to AMS
7. Connect Rules
8. Adding behavioral models of technology standard cells for simulator compiler in ADEL-- simulation -- options -- AMS simulator

This is an example of the imported netlist: (I changed the real component names to StandardCell_#)

// Created by ihdl
module xorGate_synopsys ( rst, clk, a, b, y );
input rst, clk, a, b;
output y;
wire n1, n2, n3, n4;

StandardCell_1 U2 ( .A(rst), .Z(n1) );
StandardCell_2 regxP_reg ( .D(n4), .CP(clk), .RN(n1), .Q(y) );
StandardCell_3 U6 ( .A(b), .B(n3), .C(a), .D(n2), .Z(n4) );
StandardCell_4 U7 ( .A(a), .Z(n3) );
StandardCell_5 U8 ( .A(y), .Z(n2) );
endmodule