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Schematic Pcell : internal node probing

mihirDesai

Hi,

Is it possible to probe internal nodes for a stacked Schematic pCell.

I have a stack config where multiple transistors are stacked and want to probe internal node.

When I try this through normal method it does not seem to work.

1. in the ADE XL window -> Outputs -> To BE Saved -> select on Design.

2. Then I select the internal node

But this does not add the signal in the Outputs subwindow in the ADE XL Editor.

I tried to check the netlist but it doesnot show there also.

Thanks,

Mihir

Parents
  • Andrew Beckett

    Hi Mihir,

    it may be that your schematic pcell doesn’t have the wires associated with thel nets. Strictly speaking for netlisting the connectivity is all that is required, and the physical drawing isn’t needed or if provided by the pcell doesn’t have to be completely defined the way that a hand drawn schematic would. 

    So most likely this is down to a flaw in the schematic pcell code. We could check that via customer support if we can look at the setup. One way to check is to select the wire in the schematic pcell and then in the CIW type:

    geGetSelSet()~>net~>name

    if this returns (nil) then it’s not set up correctly - compare with a normal (check-and-saved) schematic. 

    Andrew

  • mihirDesai
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks for the quick reply!

    I did run the command on one net and it does show correct net name there. Also netlisting the schematic shows correct internal nodes so I am thinking that should be fine.

    Essentially in the code I am doing the following the draw wires.

    wire = dbCreateLine(cv list("wire" "drawing")
                                      list(lx:ly ux:uy)
                                    )
    wire~>net = nl1

    Is this correct or something more needs to be done ?

    Thanks,

    Mihir

Reply
  • mihirDesai
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks for the quick reply!

    I did run the command on one net and it does show correct net name there. Also netlisting the schematic shows correct internal nodes so I am thinking that should be fine.

    Essentially in the code I am doing the following the draw wires.

    wire = dbCreateLine(cv list("wire" "drawing")
                                      list(lx:ly ux:uy)
                                    )
    wire~>net = nl1

    Is this correct or something more needs to be done ?

    Thanks,

    Mihir

Children
  • Andrew Beckett
    in reply to mihirDesai

    The fact that it netlists ok doesn’t prove anything since that only looks at the connectivity and not the link between physical objects (the wires) and the connectivity. 

    What you’ve described seems reasonable and should work. Similar constructs work fine for me. Could you contact customer support so that we can take a look (ask them to involve me if the AE can’t resolve it).

    Regards,

    Andrew

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