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  3. regarding layout netlist

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regarding layout netlist

skillEater
skillEater over 7 years ago

Hi all,

I am searching an option to export only netlist for layout in icfb.

Somebody please help me.

Thanks,

Ganesh Doddipatla.

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  • Andrew Beckett
    Andrew Beckett over 7 years ago

    What does this mean? Are you asking how to take a layout, and extract the devices from the layout and produce a netlist? If so, what format do you want the netlist in? Are you asking to produce a netlist from the connectivity information in a layout created with Virtuoso Layout Suite XL (i.e. with connectivity) - if so, why?

    I really don't understand what you're trying to do here.

    Regards,

    Andrew.

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  • skillEater
    skillEater over 6 years ago in reply to Andrew Beckett

    Hi Andrew,

    Sorry for not being clear.

    What I really want to do is genarate a spice netlist file like when we generate CDL.

    Thanks,

    Ganesh Doddipatla

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to skillEater

    OK, but a SPICE netlist (CDL isn't actually a SPICE netlist, although it's similar in syntax) is generated from the schematic not the layout.

    Do you have a schematic? It's still rather unclear to me what you have and what you're expecting to get.

    Regards,

    Andrew.

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  • skillEater
    skillEater over 6 years ago in reply to Andrew Beckett

    I want to generate layout netlist so that I can compare with the schematic netlist (LVS).

    In general this is done by physical verification tools where it is taking so much time to generate the layout.sp(layout netlist).

    I think we can reduce the run time if we have layout netlist directly from icfb  and all we have to do is comparison.

    Please tell me is this possible ??

    Thanks,

    Ganesh Doddipatla.

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to skillEater

    Hi Ganesh,

    You'll only have connectivity in the layout if it was generated with VLS XL (probably). Even then, the layout database does not get marked that the connectivity is up to date so that the design can be netlisted. However, even if I do that (which could be done using SKILL), you may also have problems if there are pins on the devices which do not have connectivity - for example the bulk pins on transistors which are connected to the substrate - often the substrate is not "connected" in VLS XL, and hence you'd have an incomplete netlist.

    So there's a lot of reasons why this would be hard to do.

    Even then, what are you comparing? Virtuoso Layout Suite XL is going to check against the schematic for what it knows about - so running LVS on a netlist produced from the layout connectivity database is not going to tell you much that VLS XL didn't already tell you. The point of a physical verification tool is to have a "signoff" tool that will extract the devices from the shapes in the layout and extract the connectivity and then compare that.

    So I don't think what you're asking for is really feasible (at least not unless there are a lot of joined up conditions), and even if you can make it work in practice I'm not sure it's going to be terribly useful as an alternative to doing a proper LVS.

    Regards,

    Andrew.

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  • skillEater
    skillEater over 6 years ago in reply to Andrew Beckett

    OK Thanks Andrew.

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