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Autostop AMS simulation when specific digital goes high

Nasser Arif

Hi,

Is it possible to stop AMS simulation when specific signal (from RTL) goes high,

We are doing calibration of some block to get the proper code from Digital side, after calibration RTL assert "done" signal.

I saw below solution, but it is based on Analog signal.

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nVHHEA2&pageName=ArticleContent&sq=0050V000006m8RVQAY_201810184711482 

I am using IUS 15.20.024

Thanks,

Nasser 

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  • Saloni Chhabra

    Hi Nasser,

    There must be multiple ways of achieving this, but a simple one could be to add a conditional $finish in the RTL. Or you could insert a separate small checker module (verilog) in the setup (so you don't have to modify the RTL) where you are checking for 'done' signal to go high. The AMS simulation will stop based on whether it sees a $finish or tran stop time first. As an example:

    module checker_autostop ( );

    always @(posedge top.dig_core.done) begin
     if($realtime>0)
         $finish;
    end

    endmodule

    Regards,

    Saloni

Reply
  • Saloni Chhabra

    Hi Nasser,

    There must be multiple ways of achieving this, but a simple one could be to add a conditional $finish in the RTL. Or you could insert a separate small checker module (verilog) in the setup (so you don't have to modify the RTL) where you are checking for 'done' signal to go high. The AMS simulation will stop based on whether it sees a $finish or tran stop time first. As an example:

    module checker_autostop ( );

    always @(posedge top.dig_core.done) begin
     if($realtime>0)
         $finish;
    end

    endmodule

    Regards,

    Saloni

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