Output busses containing shared nets yielding an error

Hi,

setting a label on a wire will set the netname. The pinname will also be taken as a netname for the connected wire. There you get your short from.

Kind regards,

Marc

I think I'm missing the subtle distinctions between labels and names (or more). What I'm trying to do, I believe, seems reasonable - maybe I should have asked what I need to do different to make this work properly...

Please explain what you try to do ( and maybe why) and I can try to explain how...if possible.  Why should the pin, have a different name than the connected wire?
If you just want to add some information, you could "Create - Note"  which is more a kind of text label which would not interfere with any design data.

Our assumption is, that if you  place a label on a net, you probably want to do that to see the name of the net and make it non-generic. Could be the wrong assumption in some cases.

Hi,

You could use the cds_thru component from basic library to connect nets of 2 output pins. See the example below:

Regards,

Dimitra

I'll try to explain what I'm trying to do, although I'll preface it by saying I'm not very well versed in Virtuoso. My simplified description showed two 3-bit output busses, but in reality they're more like 20-bit busses comprising lots of randomly named nets (collectively they serve to configure the blocks they're going to into various test modes). If I label the two output pins as a long list of comma separated net names then the symbol pin names become long and ugly, so in the schematic I attached each of the two long bus nets to pins simply named outx<20:0> and outy<20:0>. This makes the symbol look simple and at the upper level I can just route two busses each going to their respective destinations. As previously described, the issue is that those two output busses contain a few common output signals. Cosmetically, I was trying to avoid making 3 pins on the symbol - one for the unique signals going to blockX, one for the unique signals going to blockY, and one for the common signals going to both blocks. At the next level up that would have meant a bunch of bus merging etc. to achieve what I was trying to do in the first place.

I can see in Dimitra's post that I could use a cds_thru component - I can give that a try although in my mind it seems like a "hack". It still confuses me why letting some output nets leave the cell through multiple output pins is inherently illegal (who cares, so long as they all go to inputs at their destinations). 

Only so I can understand things better, would somebody please mind commenting about my thought "It still confuses me why letting some output nets leave the cell through multiple output pins is inherently illegal (who cares, so long as they all go to inputs at their destinations)."

This is mostly a historical limitation. In CDB (the old Cadence database format), there was no way of representing this - each net had at maximum a single terminal. OpenAccess does however allow multiple terminals for the same net (with different terminal names); however, to support this throughout the entire flow (schematic editor, probing, netlisting, layout editor and layout XL) would need quite a bit of work and I've not seen anyone who has had a compelling need for this that would justify all that work.

Given that many of the netlist languages wouldn't support this - SPICE simulators in general wouldn't have the concept of multiple pins all of which were connected internally - it would particularly need special support to ensure that the handling was correct - potentially the pins of the subckt wouldn't match the pins of the symbol any more and that presents another set of problems. We don't want want to automatically create pseudo short components in the netlist without the user indicating that this is expected (that's what cds_thru does), and having a mismatch between the terminals in the netlist and textual views means more work would have to be done to map pins, etc etc.

So it creates a bunch of flow and code complexity with little reward other than (mostly) cosmetic convenience on the schematic.

You can of course have multiple pins with the same name on the same net - that is possible.

Regards,

Andrew.

Perfect answer - I now understand the details. Thanks Andrew.