Missing Parameter in Layout "Edit Instance Properties"

Those warnings in the CIW are nothing to do with this - it's because you have some old ADE-related cdsenv settings in a central cdsenv in the NCSU CDK - but they are for setting up the ADE plotting window, and nothing to do with the width of the devices in the  layout.

Which parameters are displayed are entirely a function of the design kit you're using - it's not a Virtuoso choice. Looking at the screen shot you provided, the design kit appears to have been set up that you don't specify the width and length in microns, but in grid units - I expect if you change the number of grid units, it will indeed change the layout pcell. If it doesn't, you should contact NCSU as it's a feature of their design kit.

Regards,

Andrew.

Mr Andrew, thank you so much for your valuable suggestion and i appreciate. Okay i understand and i change the number of grid units, and it does not change the layout of pcell.

But, one thing i'm gonna pointed to you, earlier in my Schematic editor, during drawing schematic, i could not able to change pmos or nmos devices SIZE(width).  I noticed that all CDF parameters of pmos/nmos (including width,length, model name,drain/source diffusion area etc) option was remained empty.  It is because spectre was not enabled. So at first i checked under Option>Tool Filter.... and i enabled spectre. Then, it pops up all CDF parameters of nmos/pmos and allow me to change the width, based on my design requirements. And so far schematic editor is working fine. Only i'm facing this problem during layout.

Now my biggest fear is that, does spectre is not enabled in my layout mode? and that is why i am not seeing all those parameters in Edit Instance Properties in Layout in virtuoso 6.1.7-64b. Do you think that could a possible reason? if so, how can i resolve this issue. 

I also tested same NCSU CDK, by using in virtuoso 6.1.4, its working fine here. Pops up all the parameter of pmos/nmos devices.  Please see the attachments for details and you will see the difference.

Thanks,

John

It could be several things. I tried to access the NCSU CDK, but unfortunately this requires registration and that's broken at the moment.

Can you check the Tools->CDF->Edit CDF, pick the lib and cell for the transistor (ideally "Base") and then look for the Width parameter - check what the "display" callback expression is?

Maybe it's set (rather unusually for a PDK) to artParameterInToolDisplay('Width) or similar. Normally that's for simulation only parameters, not for something that would be in the layout.

If it's indeed set to that, can you check what:

envGetVal("auCore.toolFilter" "defaultTools")

returns? Does it contain "spectre" ?

You could try changing the default tools to:

envSetVal("auCore.toolFilter" "defaultTools" 'string "spectre auCdl auLvs")

which would also probably avoid you needing to turn it on in the Tool Filter in the schematic too. If it doesn't include spectre, it's probably been customised in your environment as the default would normally contain  spectre.

Regards,

Andrew.

Mr. Andrew big thanks!...this command/code {envSetVal("auCore.toolFilter" "defaultTools" 'string "spectre auCdl auLvs")}  solve my issue. now i can change the nmos/pmos devices parameter in layout. its working fine.

But i need one more favor from you. I can not " Flatten"  by selecting two nmos cell in virtuoso 6.1.7, using Edit > Hierarchy > Flatten. However, i can able to " Flatten"  by selecting two nmos cell  in virtuoso 6.1.4,  and then using.... Edit > Hierarchy > Flatten.  I tried several times and could not able to discover why it is not allow me to flatten of the selected two nmos cell. Please see the attachment for details and you will see the difference. 

Any advise how can i resolve this issue? OR Is there any command/code exist, that i can add into my .cdsint file and will allow me to "Flatten" two nmos cell nicely.

Thanks,

John

Not sure why you need to flatten it, but did you make sure that on the form that appears when you pick the Flatten menu has the "Pcell" entry checked? By default (in IC614 and IC617) Pcells are not flattened unless you turn this checkbox on.

Other than that, I can't see any reason why you wouldn't be able to flatten the devices. Perhaps you can upload a screenshot of the flatten form as you've filled it in (assuming the hint above doesn't solve it for you). I've never heard of anyone having issues with flatten not working provided that the form is correctly completed.

Regards,

Andrew.

Not sure why you need to flatten it, but did you make sure that on the form that appears when you pick the Flatten menu has the "Pcell" entry checked? By default (in IC614 and IC617) Pcells are not flattened unless you turn this checkbox on.

Other than that, I can't see any reason why you wouldn't be able to flatten the devices. Perhaps you can upload a screenshot of the flatten form as you've filled it in (assuming the hint above doesn't solve it for you). I've never heard of anyone having issues with flatten not working provided that the form is correctly completed.

Regards,

Andrew.

Mr. Andrew, once again big thanks!. Actually  my “Pcell” was unchecked. According to your suggestion I checked on “Pcell” and now it allow me to Flatten two NMOS cell. it’s working fine. 

Thanks,

John