Howto generate a ibis model from schematic/extracted design

This application note: IBIS characterization and modeling for IO cells explains how to generate IBIS models using Liberate.

Regards,

Andrew.

Thanks for the valuable link.

For clarification - is Librate an extra tool - do I need an extra license for it, or does it ship with Virtuoso Analog Designer ?

It's an extra (licensed) tool specifically designed for characterisation problems. I'm not aware of anything specifically that explains how to characterise IBIS using ADE. There was a paper many years ago at a couple of CDNLive events called "IBIS Generation and Validation Methodology Using Spectre MDL" by Rom Bronfman (then at Saifun). This was in 2005, and unfortunately I can't locate the proceedings that far back - but even then, this was using a command-line SpectreMDL based flow, so it's not what you're asking for either. 

Regards,

Andrew.

Well in that case I (most probably) will have to create the IBIS model in a textfile - import it in Virtuoso Analog Designer and match the IBIS behavior manually to the spice simulation results - that should be doable, right?

Or do you have any other suggestion ?

I assume so - I've not tried doing this myself (I really have little experience of IBIS generation other than reading that paper many years ago). Spectre itself has support for simulating IBIS buffer models so you can probably compare the text IBIS model with the actual circuit under a range of tests. There are articles on support.cadence.com which do talk about how to use an IBIS model in spectre in ADE, but this is more from a use rather than characterisation perspective.

Regards,

Andrew.

In case others come across this thread (like I did), it appears that IBIS model generation in Liberate is considered obsolete now and that functionality is now in part of the Sigrity suite of tools.