Cell Abutment Wiring Warning !

Hi Ranaya,

The check against source is because you're probably checking all parameters - this can be controlled by CDF properties on the device, but also globally using the Parameters tab on the Options->Layout XL form. It may not make sense to check the abutment related parameters against source because it's unlikely the schematic would have these layout-only parameters set.

Not sure what the other marker is for - you should be able to tell using the Annotation Browser.

Regards,

Andrew

Thanks for pointing out Andrew. The mark looks like an illegal weak connection. 

Mmm...  even the design passes LVS, but it's annoying to see this mark as it is not distinguishable from a short. What does this exactly indicate btw?

Ranaya

Hi Ranaya,

You can't just assume that all markers are shorts! There are a variety of different things that can be displayed in the annotation browser - you can colour them differently. It's why it make sense to use the annotation browser to see wha the issues are...

An illegal weak connection suggests that you have a component with weakly connected pins (often the pins at each end of the gate on a transistor) where you have connected to both ends of the gate. The idea of a weak connection is that you should connect one or other end, but not both - in essence you don't want to rely on connecting through a resistive internal connection in the device. Most likely the LVS rules don't check this for a transistor gate. It's not clear from the pictures what the weak connect violation actually is (you may need to contact customer support so that we can look at your data).

Regards,

Andrew.

Hi Andrew, 

So basically, the weak connection appears when I make the (circled) metal connection between the abutted contact points. These 4 transistors just form 2 transmission gates as shown in the schematic below where the metal wire connects sources of NMOSes and drains of PMOSes :

Ranaya

That looks odd - I can't see why that would be seen as a weak connect violation. I'd have to see the PDK and the example to understand this better. Maybe there's something wrong with how the pins are set up on the transistors in the PDK?

Regards,

Andrew.

What it might be is that there are both diffusion pins and metal pins on the source/drain and these are (incorrectly) set up as weakly connected (they should be strong connect). It may then see that both the metal and diffusion connections are being made and so that's the violation - but this is just a guess, I'd really need to see it to be sure.

Regards,

Andrew.