Verilog A: Error on altering 'paramerized' module

That's a bit odd, because I'd have expected that changing the schematic would definitely cause the simulator to exit and restart - which I would have assumed would have avoided this issue.

However, I did find a number of reports of this error which were fixed some time ago. Which spectre subversion are you using? This should appear at the top of the spectre log (spectre.out if using ADE) - that would be a useful piece of information to know.

As I think I've said in other posts, bsimcmg is integrated into spectre as a built-in model, so I can't really see why you'd need (or want) to use the Verilog-A model instead - the performance will undoubtedly be better with the built-in compiled model.

Regards,

Andrew.

The spectre version is: 15.1.0.727.isr15 64bit -- 22 Feb 2017.

I have to use the original BSIMCMG Verilog-A model because I am changing some of the equations in the Verilog-A code. I don't think this is possible with built-in compiled model, correct?

Let me add some more information. 

• The bsimcmg model code has a file called bsimcmg.va. This is a top level code which calls several other code files, such as common_defs.include, bsimcmg_binning_parameters.include, bsimcmg_body.include, etc.
• I created a cell and verilog view for *only* the top level bsimcmg.va. I call this cell nfinfet_va. In this cell, using the Cadence VerilogA-Editor, I added two lines: 
  • (* compact_module *)
  • (* instance_parameter_list = {TFIN, L, NFIN, NF, NRS, NRD, ASEJ, ADEJ, PSEJ, PDEJ} *) --> This is a subset of all the possible instance instance parameters listed in bsimcmg_body.include.
• The other code files are text files that do not have cell views in Cadence. They are saved as files in the same Linux directory path as the Cadence cell nfinfet_va.
• I made a minor modification to the bsimcmg_body.include, which is the addition of a white_noise source for a specific current path.

Before running any simulation, or if I make a change to either schematic or the ADE testbench, I *must* resave one of the include files in the directory. Actually, I don't have to resave, but just update the timestamp of a file (e.g. using Linux "touch bsimcmg_body.include" or "touch common_defs.include" works).

Do I need to make a Cadence cell view for each of these Verilog-A code files called by the main code?

You shouldn't need to touch the include file. That's almost certainly triggering a recompilation, but I can't see why that would be needed. So this is very strange...

So my suggestion would be to:

1. Try again with the latest hotfix (of SPECTRE17.1 or SPECTRE18.1) to see if it still happens
2. If it does, contact customer support.

Creating a view for each of the include files doesn't make sense because they are not modules in their own right.

Regards,

Andrew.