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How to run jitter tolerance analysis in cadence

usuikazou

Hi,

I am designing clock and data circuit,  I want to do jitter tolerance analysis in cadence, how to run the simulation? Is there any guide or reference to do jitter tolerance analysis in cadence virtuoso? 

I am using IC5 and IC6.

Thank you.

Parents
  • Andrew Beckett

    It rather depends on what you mean by "jitter tolerance analysis". The SpectreRF pnoise/hbnoise analysis has modes for analysing jitter (particularly shooting PSS/pnoise for switching circuits) which would probably be your best choice, and the UI for this is cleaner in later IC6.1.7 versions (together with SPECTRE 17.1).

    By asking this for both IC5 (for which the last release was in 2004, and stopped being supported in 2011) and IC6 (which could be any of 9 different major versions) your question is rather open ended...

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    It rather depends on what you mean by "jitter tolerance analysis". The SpectreRF pnoise/hbnoise analysis has modes for analysing jitter (particularly shooting PSS/pnoise for switching circuits) which would probably be your best choice, and the UI for this is cleaner in later IC6.1.7 versions (together with SPECTRE 17.1).

    By asking this for both IC5 (for which the last release was in 2004, and stopped being supported in 2011) and IC6 (which could be any of 9 different major versions) your question is rather open ended...

    Regards,

    Andrew.

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