• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Quantus QRC (PVS interface) error

Stats

  • Locked Locked
  • Replies 4
  • Subscribers 126
  • Views 15526
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Quantus QRC (PVS interface) error

mhkvy4
mhkvy4 over 6 years ago

Hello,

I am not sure if this is the right forum to post issues regarding Quantus QRC. If it isn't kindly, move the thread to the appropriate forum. 

I was trying to use Voltus FI for EMIR analysis. The rak is titled "Voltus-Fi-L EMIR Analysis Workshop". The basic flow has you do LVS with PVS followed by extraction using Quantus QRC's PVS interface. This is then used as an input to Voltus FI. The LVS ran without any issues but I get the following errors during RC extraction. 

ERROR (CAPGEN-41313): The options "-delta_gate_ckt" OR "-delta_gate_ckt_by_device" OR "res_gate_factor/res_gate_default_factor" can't be used together "exclude_gate_res". Restate input options.

ERROR (RCXSPIC-27225): /public/cadence/618/EXT182/tools/extraction/bin/64bit//capgen failed with status 25

For what it's worth I am using EXT18.2 version, not the 18.1 version. The drop down menu in the layout editor now says Quantus instead of QRC like it does in the rak. 

  • Cancel
Parents
  • Quek
    Quek over 6 years ago

    Hi mhkvy4

    You have posted to the right forum. Would you please try the following?

    a. In Quantus form, go to "Extraction" tab
    b. There is most probably a default value of "2" in "Gate Resistance Factor" field
    c. Please remove it and retry extraction


    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • mhkvy4
    mhkvy4 over 6 years ago in reply to Quek

    Yes, that made it work. Could you explain what the default value of 2 implies? I am assuming leaving it blank means gate resistance is not taken into account when doing RC extraction.

    Thanks. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Quek
    Quek over 6 years ago in reply to mhkvy4

    Hi mhkvy4

    QTS divides the calculated gate res by the specified factor. You can read more about "res_gate_default_factor" compilation option in $QRC_HOME/doc/extTechgen/extTechgen.pdf. It has a detail explanation on the option.


    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • mhkvy4
    mhkvy4 over 6 years ago in reply to Quek

    I will read the documentation. Thanks for your help. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • mhkvy4
    mhkvy4 over 6 years ago in reply to Quek

    I will read the documentation. Thanks for your help. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information