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Characterization of a transmission gate (Liberate)

Edouardfr

Hello,

I am trying to characterize a basic transmission gate (nmos and pmos in parallel, with complementary select signals, unbuffered input and output) with Liberate.

The thing is since the input is unbuffered, the input capacitance of the gate is assumed to be very large and as a result, when doing the P&R flow, the delays are very high (it takes the high values in the timing tables).

I recently read in the Liberate RAK that a TGATE is considered to be an analog cell an should not be characterized, but I am wondering what would then be the process to get its timing information for my P&R flow?

Best,

Edouard 

Parents
  • Guangjun Cao

    Hi Edouard,

    I believe the P&R experts can better answer this question. Or, is it a problem with your design flow.

    My question would be,

    1. what arcs or information do you want to put into the library?

    2. Do you know the realistic values to use for the model?

    guangjun

Reply
  • Guangjun Cao

    Hi Edouard,

    I believe the P&R experts can better answer this question. Or, is it a problem with your design flow.

    My question would be,

    1. what arcs or information do you want to put into the library?

    2. Do you know the realistic values to use for the model?

    guangjun

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