Import Schematic from Mentor Tanner to Cadence

Given that the storage format for S-Edit is EDIF (or a variant of EDIF), the best route is to use the EDIF export from the S-Edit tools and then import that into Virtuoso. I've had good success with that, although I have had to do some pre- and post-processing to clean things up - sometimes due to PDK incompatibilities, sometimes due to limitations/bugs in both EDIF interfaces (in the source and destination tool). You may want to try this and if you have trouble, please contact customer support - although it might need a service if the work needed is extensive.

Regards,

Andrew.

Thank you very much! I will give it a shot.

Hi Andrew, 

I ran into a few problems while implementing your solutions.

The following window popped up when I tried to import the EDIF. The Run Directory and Input File sections made sense to me, could you please tell me what is to be added in the other sections?

Also, when I clicked on OK, this is what happened: 

Loading cph.cxt filename - /tmp/edifTMPm25079 fullname - /tmp/edifTMPm25079 Saving setup data to -> /tmp/edifTMPm25079. Saving setup data ok checkout of edifin (940) was successful Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.01s. *WARNING* LIB Inverter from File /home/cadence/cadence/installs/IC618/share/cdssetup/cds.lib Line 8 redefines LIB Inverter from the same file (defined earlier.) *WARNING* LIB basic from File /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Line 1 redefines LIB basic from File /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/composer/cds.lib Insert UNDEFINE basic before DEFINE basic in /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Or remove or comment out DEFINE basic in /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/composer/cds.lib to suppress this warning message. *WARNING* LIB analogLib from File /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Line 2 redefines LIB analogLib from File /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib Insert UNDEFINE analogLib before DEFINE analogLib in /home/cadence/Untar/AccessRequest-TC013534_1/TN28CRSP025W1_1_0_2P2A/iPDK_CRN28HPC+_v1.0_2p2a_20170531_all/iPDK_CRN28HPC+_v1.0_2p2a_20170531/cds.lib Or remove or comment out DEFINE analogLib in /home/cadence/cadence/installs/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib to suppress this warning message. Process edifin Done -- check the file edifin.log for more information

Here's what the log file contained:

error at line :1 between 'edif' and 'Project_design' Unexpected character " " in input error on line 1: between 'edif' and 'Project_design' syntax error Translation complete. There were 0 warning messages and 2 errors in the design.

I would really appreciate any suggestions that could aid me. Thanks for going through this!

Without seeing the EDIF file, this is quite hard to debug. Perhaps you can do the following two commands in UNIX:

file Project_design.edf
head -2 Project_design.edf | cat -vet

and show me what each outputs (the second will output just the first two lines of the EDIF file, but show any unusual characters).

Regards,

Andrew.

This is what I got after keying in file Project_design.edf:

Project_design.edf: ASCII text, with CRLF line terminators

The next line, head -2 Project_design.edf|cat -vet:

(edif Project_design^M$
^I(edifVersion 2 0 0)^M$

OK, in that case you have a file with DOS (Windows) file endings. Before importing the file, do:

dos2unix Project_design.edf

Regards,

Andrew.

OK, in that case you have a file with DOS (Windows) file endings. Before importing the file, do:

dos2unix Project_design.edf

Regards,

Andrew.

Thanks a ton, Andrew! Your solution worked like a charm! 

However, the test ring oscillator that I was trying to import looked nothing like what it was supposed to:

I suppose this is due to the 'PDK incompatibilities or the limitations/bugs in both EDIF interfaces' that you mentioned earlier? In that case, is there any alternative that I could explore or would you recommend that I redraw the schematics instead? 

Thanks again for all the help!

Assuming that you wrote out the EDIF with the "Composer" option from S-Edit, then it appears there's a scaling issue. You might be able to resolve this by playing with the "Set Schematic DBUPerUU" settings on the EDIF Import form - this is really the kind of thing it would be best to work with a Cadence Application Engineer on via customer support, as having access to the EDIF file would make these kind of things easier to resolve.

I don't think there's really any other route (other than using SPICE In, which will create schematics that don't look much like your originals) to import the data.

Regards,

Andrew,