Input Capacitance Characterization in Cadence Liberate

Hi,

This is not a normal standard cell, and you may have different issues if you want to characterize it. Can you find specifications for cells of such a nature, ie. a transmission/pass gate, in the Liberty documentation?

For the specific question you raised here, please read the liberate manual on harness. It might or might not work. basically, you may put any external components into a harness. 

Regards,

Guangjun 

Thanks alot for your reply. My question should be, rather, how to characterize such a cell.

From the manual, following seem to be related to this type of behavior : 

However, it's bit unclear how these switches should be used in the script and whether they satisfy my requirement. I'll look for the "Harness" in manual.....

Anuradha

Hi Again,

I saw a similar post regarding a transmission gate type (non-standard) cell characterization issue : 
https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41066/characterization-of-a-transmission-gate-liberate

So would Liberate AMS do a better job in characterizing such non-standard cells ? 

Anuradha

It is about Liberty specification/support, not how this should be characterized. we have discussed this before. If you can find a specification for this cell in Liberty documentation, and how this cell should be characterized, please let me know.

Guangjun

Dear Gaungjun, 

Hi, sorry for bringing this post up again. But this question is related to the very "harness" example shown in Liberate manual (pg 132, Product Version 16.1, October 2017). You can take a look at it again here:

https://pastebin.com/QZrD6Xb6

This example is for an "un-buffered mux" which is quite similar to the cell type we have discussed here. This example suggests to use external input drivers (two cascaded inverters) and an external load as a wrapper to the cell that's characterized. This technique seems to solve the large input capacitance and timing errors that observed in normal characterization process. However two things are not clear (Manual doesn't explain it) :

1. Are the driving inverters in the wrapper (harness subckt) also taken into account for power measurements ?

2. When measuring the capacitance to the inputs of the actual cell, does the measurement system isolate the capacitance loading introduced by driving circuits in the wrapper ?

Looking forward to your explanation. Thanks

Anuradha

Hi Anuradha,

The example is a generic one, it is not necessary an recommendation for a particular type of cell.

1. a harness will be used to provide a driver or bias or load. power characterized based on current flowing in/out a port of you block to be characterized.

2. capacitance is characterized based on the current in/out of a port over a period of time, ie. charge. 

So, if there is current path from your power to the harness through the ports to be characterized, the characterized model might be affected.  

Regards,

Guangjun

Hi, one strange observation I find after using the input drivers in the harness, is the non-monotonicity in index1 data. Take a look at this (in the generated .lib file) :

cell_rise (delay_template_7x7_1043) {
index_1 ("0.0294363, 0.029438, 0.0293399, 0.0305652, 0.0330034, 0.0368964, 0.0424564");
index_2 ("0.001, 0.0017421, 0.00434703, 0.00932152, 0.0170715, 0.0279457, 0.0422546");
values ( \
"0.107349, 0.107349, 0.107349, 0.107349, 0.107349, 0.107349, 0.107349", \
"0.107465, 0.107465, 0.107465, 0.107465, 0.107465, 0.107465, 0.107465", \
"0.107164, 0.107164, 0.107164, 0.107164, 0.107164, 0.107164, 0.107164", \
"0.106852, 0.106852, 0.106852, 0.106852, 0.106852, 0.106852, 0.106852", \
"0.106702, 0.106702, 0.106702, 0.106702, 0.106702, 0.106702, 0.106702", \
"0.106364, 0.106364, 0.106364, 0.106364, 0.106364, 0.106364, 0.106364", \
"0.106601, 0.106601, 0.106601, 0.106601, 0.106601, 0.106601, 0.106601" \
);
}

You can see that the 3rd value in the index 1 is smaller than previous two, so this violates the slew-load combinations intended for the cell modeling. What could possibly be the reason for this ? I don't find any errors i.e. Bad CCS data, and all the cells passing the characterization. However downstream tools complain about the values in the index1.

Anuradha

Are you using -auto_index option in the char_library? if so, this looks like a bug.

Guangjun

No, I don't. You may find the settings in following : 

https://pastebin.com/kwQnDew7

Thanks 

Anuradha

if you are not using -auto_index option, then this index-1 table comes from your own definition. Please check your define_template command for this template.

Guangjun

Unfortunately not ! That's the strange thing here. Here's my definition for index-1/2 tables : 

define_template -type delay \
-index_1 {0.002 0.0120375 0.0472711 0.114555 0.21938 0.366461 0.56 } \
-index_2 {0.001 0.0017421 0.00434703 0.00932152 0.0170715 0.0279457 0.0422546 } \
delay_template_7x7_1043

define_template -type power \
-index_1 {0.002 0.0120375 0.0472711 0.114555 0.21938 0.366461 0.56 } \
-index_2 {0.001 0.0017421 0.00434703 0.00932152 0.0170715 0.0279457 0.0422546 } \
power_template_7x7_1043

I don't see the same index-1 table in the generated .lib file as I've shown earlier.....

Anuradha

this is odd. please file a support case. That is the only way I can look into this.

Regards,

guangjun

this is odd. please file a support case. That is the only way I can look into this.

Regards,

guangjun

Okay, but jut to confirm everything looks correct, can we directly assign a pre-define capacitive load like below to the output of the cell: 

//-------------------------------------------- In Harness file ------------------------------------------------------------

//ONE_B and INT are the outputs of the cell, assigning 1 fF loads between each output and GND

Coneb ONE_B_altos_out 0 1e-15

Cint INT_altos_out 0 1e-15

Or should the output load necessarily be from the index-2 capacitance values (If yes, I don't see a difference between non-harness/harness characterization, because the whole point here is to define a custom load) ?

Thanks in advance

Anuradha

Additional load can be added. it is quite common to to have a resistive load, eg. pull-up/down. For a capacitive load, you can either use a harness, or a wrapper subckt with the same cell/ports names as your original block (you need to rename the original subckt). Then, connect the C load as you want. In such a way, the C load is part of the cell to be characterized.

Is this what you want?

Regards,

Guangjun 

I think that's already been done in my harness circuit (so what I did seems correct). Regarding the odd numbers in the .lib file, I have no idea why it happens. I will file a support case for that.

Thanks for the inputs.

Anuradha