Input Capacitance Characterization in Cadence Liberate

are we still talking about the same cell? if so, you will not be able to get a valid ccs mode for such a cell. CCS model creation relies on the related PG pins, which does not exit in your case.

Guangjun

Yes Guang, it's about the same cell. But without the "harness", characterization works just fine. The only issue is the capacitance and power numbers generated by the tool were wrong. 

I was wondering whether we cannot use one of "input pins" as a PG pin to the output since output capacitance is truly excited by the input signal in this type of a cell. So end of the day, does this mean that we have no way to characterize this type of cell at all ? 

Thanks alot for all the inputs so far Guang....

Anuradha

The cell is not a standard cell. Nor is it supported by Liberty format. 

Since there is no PG pin, power does not make any sense to a downstream STA tool.

Guangjun

Hi Again,

I saw a similar post regarding a transmission gate type (non-standard) cell characterization issue : 
https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41066/characterization-of-a-transmission-gate-liberate

So would Liberate AMS do a better job in characterizing such non-standard cells ? 

Anuradha

It is about Liberty specification/support, not how this should be characterized. we have discussed this before. If you can find a specification for this cell in Liberty documentation, and how this cell should be characterized, please let me know.

Guangjun

Dear Gaungjun, 

Hi, sorry for bringing this post up again. But this question is related to the very "harness" example shown in Liberate manual (pg 132, Product Version 16.1, October 2017). You can take a look at it again here:

https://pastebin.com/QZrD6Xb6

This example is for an "un-buffered mux" which is quite similar to the cell type we have discussed here. This example suggests to use external input drivers (two cascaded inverters) and an external load as a wrapper to the cell that's characterized. This technique seems to solve the large input capacitance and timing errors that observed in normal characterization process. However two things are not clear (Manual doesn't explain it) :

1. Are the driving inverters in the wrapper (harness subckt) also taken into account for power measurements ?

2. When measuring the capacitance to the inputs of the actual cell, does the measurement system isolate the capacitance loading introduced by driving circuits in the wrapper ?

Looking forward to your explanation. Thanks

Anuradha

Hi Anuradha,

The example is a generic one, it is not necessary an recommendation for a particular type of cell.

1. a harness will be used to provide a driver or bias or load. power characterized based on current flowing in/out a port of you block to be characterized.

2. capacitance is characterized based on the current in/out of a port over a period of time, ie. charge. 

So, if there is current path from your power to the harness through the ports to be characterized, the characterized model might be affected.  

Regards,

Guangjun

Hi, one strange observation I find after using the input drivers in the harness, is the non-monotonicity in index1 data. Take a look at this (in the generated .lib file) :

cell_rise (delay_template_7x7_1043) {
index_1 ("0.0294363, 0.029438, 0.0293399, 0.0305652, 0.0330034, 0.0368964, 0.0424564");
index_2 ("0.001, 0.0017421, 0.00434703, 0.00932152, 0.0170715, 0.0279457, 0.0422546");
values ( \
"0.107349, 0.107349, 0.107349, 0.107349, 0.107349, 0.107349, 0.107349", \
"0.107465, 0.107465, 0.107465, 0.107465, 0.107465, 0.107465, 0.107465", \
"0.107164, 0.107164, 0.107164, 0.107164, 0.107164, 0.107164, 0.107164", \
"0.106852, 0.106852, 0.106852, 0.106852, 0.106852, 0.106852, 0.106852", \
"0.106702, 0.106702, 0.106702, 0.106702, 0.106702, 0.106702, 0.106702", \
"0.106364, 0.106364, 0.106364, 0.106364, 0.106364, 0.106364, 0.106364", \
"0.106601, 0.106601, 0.106601, 0.106601, 0.106601, 0.106601, 0.106601" \
);
}

You can see that the 3rd value in the index 1 is smaller than previous two, so this violates the slew-load combinations intended for the cell modeling. What could possibly be the reason for this ? I don't find any errors i.e. Bad CCS data, and all the cells passing the characterization. However downstream tools complain about the values in the index1.

Anuradha

Are you using -auto_index option in the char_library? if so, this looks like a bug.

Guangjun

No, I don't. You may find the settings in following : 

https://pastebin.com/kwQnDew7

Thanks 

Anuradha