Input Capacitance Characterization in Cadence Liberate

if you are not using -auto_index option, then this index-1 table comes from your own definition. Please check your define_template command for this template.

Guangjun

Unfortunately not ! That's the strange thing here. Here's my definition for index-1/2 tables : 

define_template -type delay \
-index_1 {0.002 0.0120375 0.0472711 0.114555 0.21938 0.366461 0.56 } \
-index_2 {0.001 0.0017421 0.00434703 0.00932152 0.0170715 0.0279457 0.0422546 } \
delay_template_7x7_1043

define_template -type power \
-index_1 {0.002 0.0120375 0.0472711 0.114555 0.21938 0.366461 0.56 } \
-index_2 {0.001 0.0017421 0.00434703 0.00932152 0.0170715 0.0279457 0.0422546 } \
power_template_7x7_1043

I don't see the same index-1 table in the generated .lib file as I've shown earlier.....

Anuradha

this is odd. please file a support case. That is the only way I can look into this.

Regards,

guangjun

Okay, but jut to confirm everything looks correct, can we directly assign a pre-define capacitive load like below to the output of the cell: 

//-------------------------------------------- In Harness file ------------------------------------------------------------

//ONE_B and INT are the outputs of the cell, assigning 1 fF loads between each output and GND

Coneb ONE_B_altos_out 0 1e-15

Cint INT_altos_out 0 1e-15

Or should the output load necessarily be from the index-2 capacitance values (If yes, I don't see a difference between non-harness/harness characterization, because the whole point here is to define a custom load) ?

Thanks in advance

Anuradha

Additional load can be added. it is quite common to to have a resistive load, eg. pull-up/down. For a capacitive load, you can either use a harness, or a wrapper subckt with the same cell/ports names as your original block (you need to rename the original subckt). Then, connect the C load as you want. In such a way, the C load is part of the cell to be characterized.

Is this what you want?

Regards,

Guangjun 

I think that's already been done in my harness circuit (so what I did seems correct). Regarding the odd numbers in the .lib file, I have no idea why it happens. I will file a support case for that.

Thanks for the inputs.

Anuradha