Importing Parasitic Netlist to Virtuoso (Wrong Model Name)

Hi Anuradha,

Because there is no subtype in the CDL netlist defined for the capacitors, it picks the default "CAPACITOR" and creates a property called subtype and model with that value. If you don't want this, add in the User Prop Mapping:

model dummy subtype dummy2

that will map both the properties to new names (dummy and dummy2) and will avoid the problem you're seeing.

Andrew.

One more question related to the same scenario:

I tried to perform a monte carlo (MC) simulation on a custom made standard cell with its extracted RC parasitics (see below settings) and a cell imported from above netlist. According to the documentation, the extraction mode of the .cir netlist is similar to following settings. With these settings I created a Calibre view for the custom cell.

In the simulation environment, I set the starting view to be "Calibre" and the stope view to be "Spectre", so that both cells are available with their parasitics. And by that I expect a fair comparison between two cells.

With process-mismatch variations enabled, I only see the variations in the waveform for my custom cell and not the cell in cir netlist. I also see that “mf” flag of the transistors in .cir netlist is set to 1. For some reason, the waveforms of .cir cell for all the iterations look superimposed without any variations (even for low VDDs). Moreover I selected all the top level schematic blocks (of both cells) to be included for MC. What could possibly go wrong here ?

Anuradha

Hi Anuradha,

I'm not sure I entirely understand what your monte carlo setup looks like (I can't answer the questions about Calibre since that's a Mentor tool and I don't have access to it), but you shouldn't need to explicitly list the blocks to be included for monte carlo. The only time you typically do that is if you have multiple test benches and need the Design Under Test (DUT) to correlate between test benches.

For the cir netlist are you including that or have you imported it into a schematic? It's really not clear what you've done here.

Maybe contacting customer support would be wise so that an application engineer can take a look at your setup? That's probably a lot easier than asking lots of questions to understand what you've done.

Andrew.

Hi Andrew,

>> For the cir netlist are you including that or have you imported it into a schematic? It's really not clear what you've done here.

Yes, I have a Symbol OA library for std cells. So I imported the cir netlist with R/C as dummy models and subtypes (as was suggested). End of the day, all the cells in OA library have mosfets and associated parasitic components. 

I'll contact customer support for further assistance....

Anuradha

Okay, the issue seems to be in the Spice-In. The "total width" cdf parameter of FETS has not been updated and it remains in its default value. Since this is relatively a larger value, the MC variation is not significant. 

In the cir netlist, the parameters were defined in upper case:

M0 N_Z_M0_d N_A_M0_g N_VSS_M0_s N_VBN_M0_b N_12_LLRVT L=6e-08 W=3e-07
+ AD=5.25e-14 AS=5.25e-14 PD=9.5e-07 PS=9.5e-07 NRD=0 NRS=0 SA=1.75e-07
+ SB=1.75e-07 SCA=54.3776 SCB=0.0318625 SCC=0.00781068 $X=0.27 $Y=0.35

Even if I place PropMap := W w L l in devMap file,  the correct W value is not assigned to "total_width". "Trigger CDF Parameter Callback" is also enabled in spiceIn (in IC 6.1.7). Any workaround for this ?

Anuradha 

Okay, the issue seems to be in the Spice-In. The "total width" cdf parameter of FETS has not been updated and it remains in its default value. Since this is relatively a larger value, the MC variation is not significant. 

In the cir netlist, the parameters were defined in upper case:

M0 N_Z_M0_d N_A_M0_g N_VSS_M0_s N_VBN_M0_b N_12_LLRVT L=6e-08 W=3e-07
+ AD=5.25e-14 AS=5.25e-14 PD=9.5e-07 PS=9.5e-07 NRD=0 NRS=0 SA=1.75e-07
+ SB=1.75e-07 SCA=54.3776 SCB=0.0318625 SCC=0.00781068 $X=0.27 $Y=0.35

Even if I place PropMap := W w L l in devMap file,  the correct W value is not assigned to "total_width". "Trigger CDF Parameter Callback" is also enabled in spiceIn (in IC 6.1.7). Any workaround for this ?

Anuradha