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Layout instances and terminals do not match the source(No layout master defined).

FormerMember
FormerMember

Hi,

I am designing a new PDK/Tech file. Tech file is uploaded in CIW and layers looks fine in Layout suite. But when I open Layout from Schematic or generate from source, I cannot see any layout instances except gnd and vdd.  The following warnings 

Layout instances and terminals do not match the source

Cannot create a layout instance from schematic instance M0 because there is no layout master defined.    

Can someone please help me?

Kind Regards,

Waqas

Parents
  • Andrew Beckett

    Hi Waqas,

    First of all, posting this in the Feedback, Suggestions, and Questions forum is not where to ask technical questions since it's about feedback, suggestions and questions about the forums as a whole, not about any specific technical issue. So I moved it into the right forum. You'd also be wise to read the Guidelines for the Custom IC Design Forum too when posting future questions (in the right place)!

    Do your PDK components (that are in your schematic) have a layout view? In those layout views, are there pins for each of the pins on the symbol? Are the layout views (if they exists) pcells (parameterised cells) - this isn't a requirement, but I'm just asking to understand what might be wrong.

    This would probably be something better dealt with by customer support as seeing what you've done would be a whole lot easier than repeated questions via a public forum.

    Regards,

    Andrew.

  • FormerMember
    FormerMember in reply to Andrew Beckett

    Hi Andrew,

    Sorry for posting in the wrong section. Yes, I do have a graphical Pcells for resistor, and capacitor and Skill pcell for a transistor. Pins are there in layout view for each of the pins in a schematic/symbol. Sure, I will contact support. Thanks for your help anyway.

    Regards,

    Waqas

Reply
  • FormerMember
    FormerMember in reply to Andrew Beckett

    Hi Andrew,

    Sorry for posting in the wrong section. Yes, I do have a graphical Pcells for resistor, and capacitor and Skill pcell for a transistor. Pins are there in layout view for each of the pins in a schematic/symbol. Sure, I will contact support. Thanks for your help anyway.

    Regards,

    Waqas

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