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ADEXL Monte Carlo simulation and dumping sim data to a txt file

Hi,

I need to run MC simulation, say 100 runs, and for every single run of these 100 I want to keep saving a voltage to a text file, for ex. at the system clock and I want to do this as the simulation is running. It would be convenient to keep all files in the same directory of my choice, and not in the respective MC run directories. I know how to do the file saving part. What I can't figure out is how to name the files such that they don't over-write each other. Is there anything specific to the individual MC runs that I can include in the file name and how can I access that specific information from the simulation? For example, if I can include the MC run number it would solve the problem. Or maybe something else that distinguishes one MC run from another.

Thanks in advance.

Andrew Beckett over 6 years ago

It would help somewhat if you explain how you're planning to write the files...

Andrew.
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Svilen Mintchev over 6 years ago in reply to Andrew Beckett

Hi Andrew,

The way I usually do is by defining a string variable in ADEXL, say file_name to which I assign the dir path and file name by using sprintf.

(sprintf nil "/home/data/%s_%s.dat" testname,runnote)

testname and runnote are also variables.

I will need to add something to the file name thus defined to distinguish files from separate MC runs.

Then, in a verilogA block I use the conventional way of defining a string parameter, for ex. filename which takes the variable from ADEXL. Also in that verilogA I use $fopen, $fstrobe and $fclose to write to that file.

I've used that before and it works for corner simulations but now I need to do it in a MC simulation.

Thanks for helping.
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Svilen Mintchev over 6 years ago in reply to Svilen Mintchev
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Andrew Beckett over 6 years ago in reply to Svilen Mintchev

Not sure what the blank post was for. Anyway, perhaps you could use $cds_get_mc_trial_number() in your Verilog-A code? It would have been useful if you'd mentioned in your original post that you were writing data using Verilog-A - that was a rather important fact that was missing.

Andrew.
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