How to fix *WARNING* The number of errors was detected in Extract Tab: 1 in Calibre QRC run.

  Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
15.1.4-s005 Fri Nov 20 15:19:16 PST 2015
-------------------------------------------------------------------------------------------------------------------
                                    Copyright 2015 Cadence Design Systems,
Inc.

WARNING (LBRCXM-624): Warning [input]: Line 6: 'well' statement is ignored in ICT file line.

WARNING (LBRCXM-624): Warning [input]: Line 7: 'well' statement is ignored in ICT file line.

INFO (LBRCXM-630): Starting extraction: Sun Mar 10 04:33:06 2019


ERROR (AGDPRP-31003): can't open /home/marben/Documents/r1_pin_xy.spi

INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
 agdsPrep -V -rundir /home/marben/Documents -outdir /home/marben/Documents/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/Documents/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile

Forking: agdsPrep -V -rundir /home/marben/Documents -outdir /home/marben/Documents/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/Documents/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile
ERROR (LBRCXM-633): Bad return status from RCX script generator. Status 256

INFO (LBRCXM-709): *****  Quantus QRC terminated abnormally  *****

  Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
15.1.4-s005 Fri Nov 20 15:19:16 PST 2015
-------------------------------------------------------------------------------------------------------------------
                                    Copyright 2015 Cadence Design Systems,
Inc.

WARNING (LBRCXM-624): Warning [input]: Line 6: 'well' statement is ignored in ICT file line.

WARNING (LBRCXM-624): Warning [input]: Line 7: 'well' statement is ignored in ICT file line.

INFO (LBRCXM-630): Starting extraction: Sun Mar 10 05:31:52 2019


ERROR (AGDPRP-31003): can't open /home/marben/Documents/r1_pin_xy.spi

INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
 agdsPrep -V -rundir /home/marben/Documents -outdir /home/marben/query_output/query_output/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile

Forking: agdsPrep -V -rundir /home/marben/Documents -outdir /home/marben/query_output/query_output/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile
ERROR (LBRCXM-633): Bad return status from RCX script generator. Status 256

INFO (LBRCXM-709): *****  Quantus QRC terminated abnormally  *****

//  Calibre v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017
//  Calibre Utility Library   v0-2_8-2016-2    Tue Feb 9 23:45:01 PST 2016
//  Litho Libraries v2017.1_34.33  Wed Apr 5 14:22:19 PDT 2017
//
//        Copyright Mentor Graphics Corporation 1996-2017
//                       All Rights Reserved.
//   THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
//      WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
//        OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
//
//  Mentor Graphics software executing under x86-64 Linux
//
//  Running on Linux eda 2.6.32-754.9.1.el6.x86_64 #1 SMP Thu Dec 6 08:02:15 UTC 2018 x86_64 glibc 2.12/NPTL 2.12
//  Processor Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz [062a7]
//  64 bit virtual addressing enabled
//  Running aoi_cal_2017.1_34.33/pkgs/icv/pvt/calibre -query /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb pcd_inv_L -query_input query_cmd
//  Process ID: 11542
//
//  Starting time: Sun Mar 10 05:58:24 2019
//
//  Running on 1 CPU 
//

//  Applying licensing policy...
//  mgc_s license acquired (calibreqdb requested).

//  Licensed Products
//  -----------------
//  Other products:
//  - Query Server

--- CALIBRE::HDB QUERY SERVER --- Sun Mar 10 05:58:24 2019
|-------------------------------- READING PHDB --------------------------------|
################################################################################
--------------------------------------------------------------------------------
-    HDB FOR LAYOUT PRIMARY: "pcd_inv_L" WAS RESTORED FROM SVDB: /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb
-    CROSS REFERENCE WAS RESTORED FROM SVDB: /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb
-    CPU TIME = 1  REAL TIME = 1  LVHEAP = 80/82/82 MALLOC = 55/55/55
--------------------------------------------------------------------------------


--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-----          CALIBRE::HDB QUERY SERVER - EXECUTIVE MODULE                -----
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

INITIATING HDB QUERY SERVER:
--------------
   OK: Ready to serve.
ECHO
   OK: Echo is ON
status
Status 1000
Entries:
0 0 14 Mar 10 05:58:25 2019
Client: 0
View cell: pcd_inv_L
Query instance: (null)
Query cell: pcd_inv_L
Response mode: (direct)
Marker size: 0.25
Maximum vertex count: 4096
Filter distance: 0
Filter layers: (all)
Filter devices: (all)
Filter windows: (none)
Filter cull: X=0 Y=0
Magnify results: 1.0 (default value)
Rotate results: 0.0 (default value)
ReflectX results: Disabled
Translate results: Not Active
PHDB: HIERARCHICAL created with Calibre Version v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017
XDB: HIERARCHICAL created with Calibre Version v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017
END OF RESPONSE
0 0 0 Mar 10 05:58:25 2019
   OK.

## Note that the output directory and file name prefix are consistent
## for all output files. This is an important consideration for running
## QRC with the Calibre input data.
## The QRC input_db -directory_name command argument equates to the
## query output directory (query_output)
## The QRC input_db -run_name command equates to the file name
## prefix (Design) for all query output files.

## CALIBRE QUERY SERVER Script for HCCI

   gds         netprop     number   5
   OK.
   gds         placeprop   number   6
   OK.
   gds         devprop     number   7
   OK.

## Write out GDS Map

   response    file                       query_output/Design.gds.map
   OK.
   gds	       seed property device original
   OK.
   gds         map
   OK.
   response    direct
   OK.

## Write the AGF File (Annotated GDS File)

#  GDS UNITS 1 0.000000001   # only avaialble since Calibre 2006.3 release
   gds         write                      query_output/Design.agf
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## Include trivial pins and empty cells in the layout netlist
## Use only Node Numbers for netlists
## Do not write empty subcircuits for generic devices

   layout      netlist     trivial pins   YES
   OK.
   layout      netlist     empty cells    YES
   OK.
   layout      netlist     names          NONE
   OK.
   layout      netlist     primitive device subckts  NO
   OK.

## Write the Node to Net Name mapping

   layout      nametable   write          query_output/Design.lnn
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## Write a Layout Netlist with Hierarchy and $PIN_XY info

   layout      netlist     hierarchy      AGF
   OK.
   layout      netlist     pin locations  YES
   OK.
   layout      netlist     write          query_output/Design_pin_xy.spi
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## If LVS was run with LVS PUSH DEVICES SEPARATE PROPERTIES YES
## then uncomment nextline to write the separate  properties file
## Query log file will produce NOK pin location message which can be ignored

## layout separated properties write query_output/Design.props

## Write X feference file
## Write the source and layout placement hierarchy files (sph,lph) 

## Default behavior is "ON" for both xref xname layout and schematic,
## which inserts extra "X" for every hierarchy. This is desired for 
## extracted view (qrc deals with it automatically) and Ultrasim 
## stitching flow. For cell level timing analysis flow where verilog 
## does not have extra "X", users can turn on below two options.
#   xref xname layout ON
#   xref xname source OFF

   source       hierarchy   write         query_output/Design.sph

//  Applying licensing policy...
//  mgc_s license acquired (calibreci requested).

//  Licensed Products
//  -----------------
//  Base products running on 1 core:
//  - Calibre Connectivity Interface
//  Other products:
//  - Query Server
   OK.
   layout       hierarchy   write         query_output/Design.lph
   OK.

## Write Cross Reference Files
   net         xref        write          query_output/Design.nxf BOX
   OK.
   instance    xref        write          query_output/Design.ixf
   OK.

## Write the TOP Level and CELL Level Port Tables
   port        table       write          query_output/Design.ports
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.
   port        table cells write          query_output/Design.ports_cells
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## Generate Device Table for all device info
   response    file 			  query_output/Design.devtab
   OK.
   device      table
   OK.
   response    direct
   OK.

## Report LVS settings
   lvs settings report write                query_output/Design.lvs_settings
   OK.

   terminate
   OK: Terminating.

HDB QUERY SERVER terminated: CPU TIME = 2  REAL TIME = 2  LVHEAP = 1/7/82 MALLOC = 52/52/57

--- CALIBRE::HDB QUERY SERVER COMPLETED - Sun Mar 10 05:58:27 2019
--- TOTAL CPU TIME = 2  REAL TIME = 2  LVHEAP = 1/7/82  MALLOC = 52/52/57  ELAPSED TIME = 3

#! tvf
namespace import tvf::*

VERBATIM {
MASK SVDB DIRECTORY svdb QUERY CCI
/*
###############################################################################################
#
# GLOBALFOUNDRIES Singapore Pte. Ltd.
#
# File:                 cmos55lpe.lvs.cal
# Description:          Mentor Calibre LVS Runset for CMOS55LPE/RF Process
# Document ID:          EDA-CAD-55N-LV035
# Document Revision:    15
# Author:               Raju Mani
# Date:                 2016-07-31 21:32:43
#
###############################################################################################
# Copyright (c) 2016 GLOBALFOUNDRIES Singapore Pte. Ltd.
###############################################################################################
# This document is confidential and a proprietary product of GLOBALFOUNDRIES Singapore Pte. Ltd.
# Any unauthorized use, reproduction or transfer of this document is strictly prohibited.
###############################################################################################
# Disclaimer:
# -----------
# The information contained herein is confidential and is the property of GLOBALFOUNDRIES and/or
# its licensors.  GLOBALFOUNDRIES reserves all proprietary, design, manufacturing, reproduction,
# use, sales and other rights in the information herein, in its products and services, and to any
# article or process utilizing such information, except to the extent that rights are expressly 
# granted to others.
# This document is for informational purposes only, is current only as of the date of publication
# and is subject to change by GLOBALFOUNDRIES at any time without notice.  While precautions have
# been taken in the preparation of the information herein, it may contain technical inaccuracies,
# omissions and typographical errors. GLOBALFOUNDRIES is under no obligation to update or otherwise
# correct this information.  
# All information contained herein is provided "AS IS."  GLOBALFOUNDRIES makes no representations
# and disclaims all warranties of any kind, express or implied, including without limitation any 
# implied warranties of non-infringement, merchantability or fitness for a particular purpose, 
# with respect to the information contained HEREIN.   
# Terms and conditions applicable to the purchase, quality and use of GLOBALFOUNDRIES' products 
# and services are as set forth in your organization's signed agreement with GLOBALFOUNDRIES or 
# in GLOBALFOUNDRIES' Standard Terms and Conditions of Sale.  Unless otherwise authorized in a 
# signed agreement with GLOBALFOUNDRIES, GLOBALFOUNDRIES' products and services are NOT intended 
# for use in applications such as implantation, life support, or other hazardous uses where 
# malfunction could result in death, bodily injury, or catastrophic property damage.
# GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of 
# GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. Other product or service
# names are for identification purposes only and may be trademarks or service marks of their 
# respective owners.
# � GLOBALFOUNDRIES Inc. 2015. Unless otherwise indicated, all rights reserved. 
# Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES.
# 
###############################################################################################
*/
}

VERBATIM {
}


VERBATIM {
//*******************************************************************//
// Header Section                                                    //
//*******************************************************************//

//*******************************************************************//
// SWITCHES FOR THIS CALIBRE LVS DECK                                //
//*******************************************************************//

//*******************************************************************//
// METALLIZATION OPTIONS                                             //
//*******************************************************************//
// You MUST uncomment ONE metallization option.
// For more information see Table 2-7, Preferred Metallization options, in the
// Design Manual.
//
//                  a = # of 1x Thin  layers
//             	  b = # of 2x low-K layers
// a_bc_de_fg:      c = # of 2x FTEOS layers
//                  d = # of 4x low-K layers
//                  e = # of 4x FTEOS layers
//                  f = # of 12x TEOS layers
//                  g = # of 12x FTEOS layers
//
// Top Metal is always LB.
//
//*******************************************************************//
// Uncomment 1 Metallization Option OR use environmental variable BEOL_STACK
//*******************************************************************//
//

//#DEFINE 5_00_01_00_LB    //(M1, M2, M3, M4, M5, EA, LB)
//#DEFINE 6_00_01_00_LB    //(M1, M2, M3, M4, M5, M6, EA, LB)
//#DEFINE 4_02_00_00_LB    //(M1, M2, M3, M4, BA, BB, LB)
//#DEFINE 5_02_00_00_LB    //(M1, M2, M3, M4, M5, BA, BB, LB)
//#DEFINE 6_02_00_00_LB    //(M1, M2, M3, M4, M5, M6, BA, BB, LB)
//#DEFINE 4_00_02_00_LB	   //(M1, M2, M3, M4, EA, EB, LB)
//#DEFINE 5_00_02_00_LB	   //(M1, M2, M3, M4, M5, EA, EB, LB)
//#DEFINE 6_00_02_00_LB	   //(M1, M2, M3, M4, M5, M6, EA, EB, LB)

//RF-Only Metal Options
//#DEFINE 5_00_01_10_LB		//(M1, M2, M3, M4, M5, EA, OI, LB)
//#DEFINE 6_00_01_10_LB		//(M1, M2, M3, M4, M5, M6, EA, OI, LB)
//#DEFINE 5_00_00_10_LB    //(M1, M2, M3, M4, M5, OI, LB)
//#DEFINE 5_01_00_10_LB    //(M1, M2, M3, M4, M5, BA, OI, LB)
//#DEFINE 6_01_00_10_LB    //(M1, M2, M3, M4, M5, M6, BA, OI, LB)

//Alternative Metal Options
//#DEFINE 5_01_00_00_LB		//(M1, M2, M3, M4, M5, BA, LB)
//#DEFINE 6_01_00_00_LB		//(M1, M2, M3, M4, M5, M6, BA, LB)
//#DEFINE 7_01_00_00_LB		//(M1, M2, M3, M4, M5, M6, M7, BA, LB)

}

if [ info exists env(INCLUDE_FILE) ] {
        VERBATIM {INCLUDE $INCLUDE_FILE}
} else {
#        VERBATIM {INCLUDE $TECHDIR/LVS/sample_design.inc.cal}
} 

VERBATIM {
#IFDEF $BEOL_STACK 5_00_00_10_LB  
      #DEFINE 5_00_00_10_LB
#ELSE
#IFDEF $BEOL_STACK 5_00_01_10_LB  
      #DEFINE 5_00_01_10_LB
#ELSE
#IFDEF $BEOL_STACK 6_00_01_10_LB  
      #DEFINE 6_00_01_10_LB
#ELSE
#IFDEF $BEOL_STACK 6_00_02_00_LB  
      #DEFINE 6_00_02_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_00_01_00_LB  
      #DEFINE 5_00_01_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_00_02_00_LB  
      #DEFINE 5_00_02_00_LB
#ELSE
#IFDEF $BEOL_STACK 6_00_01_00_LB  
      #DEFINE 6_00_01_00_LB
#ELSE
#IFDEF $BEOL_STACK 4_00_02_00_LB  
      #DEFINE 4_00_02_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_02_00_00_LB  
      #DEFINE 5_02_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 6_02_00_00_LB  
      #DEFINE 6_02_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 4_02_00_00_LB  
      #DEFINE 4_02_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_01_00_10_LB  
      #DEFINE 5_01_00_10_LB
#ELSE
#IFDEF $BEOL_STACK 6_01_00_10_LB  
      #DEFINE 6_01_00_10_LB
#ELSE
#IFDEF $BEOL_STACK 5_01_00_00_LB  
      #DEFINE 5_01_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 6_01_00_00_LB  
      #DEFINE 6_01_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 7_01_00_00_LB  
      #DEFINE 7_01_00_00_LB
#ELSE
       SVRF ERROR "\n\n\n\t  _____NO_VALID_METAL_STACK_OPTION_DEFINED_____  \n\n\n                                   \t\t  Valid options for BEOL_STACK are:               \n\n                                 \t\t\t  5_00_01_10_LB         \n\n                                 \t\t\t  5_00_00_10_LB                       \n\n                                \t\t\t  6_00_02_00_LB                                \n\n                                \t\t\t  5_00_01_00_LB                                \n\n                                \t\t\t  5_00_02_00_LB                                \n\n                                \t\t\t  6_00_01_00_LB                                \n\n                                \t\t\t  4_00_02_00_LB                                \n\n                                \t\t\t  5_02_00_00_LB                                \n\n                                \t\t\t  4_03_00_00_LB                                \n\n                                \t\t\t  6_02_00_00_LB                                \n\n                                \t\t\t  4_02_00_00_LB					\n\n				   \t\t\t  5_01_00_10_LB				\n\n				   \t\t\t  6_01_00_10_LB				\n\n				   \t\t\t  5_01_00_00_LB				\n\n				    \t\t\t  6_01_00_00_LB				\n\n				     \t\t\t  7_01_00_00_LB	                          \n\n  "        
#ENDIF // 7_01_00_00_LB
#ENDIF // 6_01_00_00_LB
#ENDIF // 5_01_00_00_LB
#ENDIF // 6_01_00_10_LB
#ENDIF // 5_01_00_10_LB
#ENDIF // 4_02_00_00_LB
#ENDIF // 6_02_00_00_LB
#ENDIF // 5_02_00_00_LB
#ENDIF // 4_00_02_00_LB
#ENDIF // 6_00_01_00_LB
#ENDIF // 5_00_02_00_LB
#ENDIF // 5_00_01_00_LB
#ENDIF // 6_00_02_00_LB
#ENDIF // 6_00_01_10_LB
#ENDIF // 5_00_01_10_LB
#ENDIF // 5_00_00_10_LB
 }

VERBATIM {
//*******************************************************************//

//*******************************************************************//
// SWITCHES - see documentation for description and proper usage     //
//*******************************************************************//


////////////////////////////////////////////////////////////////////
//                     Custom Switches                            //
////////////////////////////////////////////////////////////////////
// ***NOTE: Refer to the Calibre LVS release notes to learn how to
//          set these new environmental variables.***
////////////////////////////////////////////////////////////////////
//*******************************************************************//
//
//
// This option is used to not compare device properties.
// Uncomment this option if you do not want property comparison. 
// Be careful using this.
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $NO_TRACE_PROPERTY = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE NO_TRACE_PROPERTY
//
#IFDEF $NO_TRACE_PROPERTY TRUE
  #DEFINE NO_TRACE_PROPERTY
#ENDIF

// This option is used to NOT compare FET nf property.
// Use this option if you do not want nf property comparison. 
// Be carefull using this.
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $CHECK_NUMBER_OF_FINGERS = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE IGNORE_NF_PARAM
//

#IFDEF $CHECK_NUMBER_OF_FINGERS FALSE
	#DEFINE IGNORE_NF_PARAM
#ENDIF

//*******************************************************************//
// This option is used to compare TIEDOWN DIODES tdndsx/tdpdnw 
// Area and Perimeter properties.
// Use this option if you want A and perim property comparison. .
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $CHECK_TIEDOWN_PARAM = TRUE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE CHECK_TIEDOWN_PARAM
//

#IFDEF $CHECK_TIEDOWN_PARAM TRUE
	#DEFINE CHECK_TIEDOWN_PARAM
#ENDIF

//
//*******************************************************************//
// This option is used not to compare pccrit property of FETs or not.
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $IGNORE_PCCRIT_PARAM = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
// Hardcoded to TRUE because pccrit is not supported in the technology.
#DEFINE IGNORE_PCCRIT_PARAM
//
#IFDEF $IGNORE_PCCRIT_PARAM  TRUE
   #DEFINE IGNORE_PCCRIT_PARAM
#ENDIF
		
//*******************************************************************//
//
// To run PEX, define "PEX_RUN"
// To run LVS, do not define "PEX_RUN" 
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $PEX_RUN = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE PEX_RUN
// 
#IFDEF $PEX_RUN TRUE
  #DEFINE PEX_RUN
  #IFDEF $CORNERROUNDING TRUE
    #DEFINE CORNERROUNDING    // corner rounding is only valid when PEX_RUN is set to TRUE
  #ENDIF
#ENDIF	
	
//*******************************************************************//
//
// To run ERC, define "ERC_RUN"
//
// $ERC_RUN = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE ERC_RUN
//
#IFDEF $ERC_RUN TRUE
  #DEFINE ERC_RUN
#ENDIF

//*******************************************************************//
//
// Series MOS reduction is not permitted by Default
// Uncomment the switch below if user wants to reduce sreies MOS devices
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $REDUCE_SERIES_MOS = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
//#DEFINE REDUCE_SERIES_MOS
// 
#IFDEF $REDUCE_SERIES_MOS TRUE
  #DEFINE REDUCE_SERIES_MOS
#ENDIF

//*******************************************************************//
//
// Split gate MOS reduction is not permitted by Default
// Uncomment the switch below if user wants to reduce sreies MOS devices
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $REDUCE_SPLIT_GATES = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
//#DEFINE REDUCE_SPLIT_GATES
// 

#IFDEF $REDUCE_SPLIT_GATES TRUE
  #DEFINE REDUCE_SPLIT_GATES
#ENDIF

//*******************************************************************//
//
// LVS recognize RX FILL as RX drawing by default.
// Uncomment the switch below if user wants to exclude RX FILL as drawing
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $EXCLUDE_RX_FILL = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
//#DEFINE EXCLUDE_RX_FILL
// 

#IFDEF $EXCLUDE_RX_FILL TRUE
  #DEFINE EXCLUDE_RX_FILL
#ENDIF

//*******************************************************************//
//
// By default,LVS use 2K high-Rs p+ poly resistor
// To define 1K p+ poly resistor,please use the following environmental variable:
//
//    $POLY_HIGH_RES =  [1K || 2K]
//
//    e.g.
//    setenv POLY_HIGH_RES 1K # [1K || 2K]
//
//========================================================================================================//
// If environmental variables are being used, do NOT edit the next lines!                                 //
//========================================================================================================//
// #DEFINE POLY_HIGH_RES_1K // Uncomment this line to extract 1K p+ poly resistor
//
#IFDEF $POLY_HIGH_RES 1K
   #DEFINE POLY_HIGH_RES_1K
#ENDIF // $POLY_HIGH_RES
//

//*******************************************************************//


//*******************************************************************//
// Include files                                                     //
//*******************************************************************//
// General calibre tool options which users are required to set have
// been move to design include file, please use $INCLUDE_FILE to locate
// user include file, by default sample_design.inc.cal will be included.
// INCLUDE $TECHDIR/LVS/sample_design.inc.cal
#IFDEF $TECHDIR
#ENDIF
   
}

VERBATIM {
//*******************************************************************//
// Description Section                                               //
//*******************************************************************//

//INCLUDE $TECHDIR/LVS/Include/cmos55lpe.extract.cal_ind
//INCLUDE $TECHDIR/LVS/Include/cmos55lpe.layers.cal_ind
INCLUDE $TECHDIR/LVS/Include/cmos55lpe.extract.cal
INCLUDE $TECHDIR/LVS/Include/cmos55lpe.compare.cal
INCLUDE $TECHDIR/LVS/Include/cmos55lpe.layers.cal

LVS FILTER D(diodepwtw) OPEN
LVS FILTER D(diodetwx) OPEN
LVS FILTER D(diodenwx) OPEN
LVS FILTER D(diodenx) OPEN
LVS FILTER D(diodepnw) OPEN
LVS FILTER D(diodedgnx) OPEN
LVS FILTER D(diodedgpnw) OPEN
LVS FILTER D(diodehvpwtw) OPEN
LVS FILTER D(diodeisotwx) OPEN
	
LVS SOFTCHK nband CONTACT
LVS SOFTCHK psub CONTACT
 
LVS SOFTCHK nw_no_n3 CONTACT
LVS SOFTCHK nw_n3_t3 CONTACT

#IFDEF ERC_RUN
   ERC SELECT CHECK FLOATING_CHKs
#ENDIF
ERC RESULTS DATABASE "./ERC_results.asc"
ERC SUMMARY REPORT "./ERC_results.rep"

//*******************************************************************//
// SET Series & Parallel STATEMENTS                                  //
//*******************************************************************//

#IFNDEF REDUCE_SPLIT_GATES
   LVS REDUCE SPLIT GATES NO
#ENDIF

LVS REDUCE SEMI SERIES MOS             NO  //YES
LVS REDUCE SERIES MOS                  NO  //YES

LVS REDUCE PARALLEL BIPOLAR            YES //YES
LVS REDUCE PARALLEL CAPACITORS         YES //YES
LVS REDUCE PARALLEL DIODES             YES //YES
LVS REDUCE PARALLEL MOS                YES //YES
LVS REDUCE PARALLEL RESISTORS          YES //YES

LVS REDUCE SERIES CAPACITORS           YES //YES
LVS REDUCE SERIES RESISTORS            YES //YES

LVS REDUCE D(tdpdnw) PARALLEL YES 
LVS REDUCE D(tdndsx) PARALLEL YES
LVS REDUCE D(tddgpdnw) PARALLEL YES 
LVS REDUCE D(tddgndsx) PARALLEL YES


//*******************************************************************//
// END SET REDUCE STATEMENTS                                         //
//*******************************************************************//


//*******************************************************************//
// Set TRACE Tolerances - Do Not Change                              //
//*******************************************************************//

VARIABLE trace_hg 2.5e-9
VARIABLE trace_int 0.5
VARIABLE trace_area 1e-15

//*******************************************************************//
// End of Header Section                                             //
//*******************************************************************//

//********************************************************************//
// END OF FILE                                                       //
//********************************************************************//

}