Stats

  • Locked Locked
  • Replies 26
  • Subscribers 126
  • Views 34558
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to fix *WARNING* The number of errors was detected in Extract Tab: 1 in Calibre QRC run.

Marben

Hi All,

I am trying to run Calibre Quantus QRC,

First I make a QRC command file name "tech.def".

Here is my code:
DEFINE pex_tech /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed

process_technology
-technology_library_file /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/tech.def
-technology_name pex_tech
-ruleset_name /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/lvsfile

But I have an error in CIW like this:

*WARNING* The number of errors was detected in Extract Tab: 1

I also got an error in CIW like this.

Please help me.

Best regards,

Marben

Parents

  • Hi Marben

    If you are doing cap extraction, you need to specify a ground net in "Extraction" tab. You can choose the largest available ground net in the layout, e.g. VSS, AVSS, DVSS, GND, AGND, etc. Alternatively, you can specify universal ground "0" too.


    Best regards
    Quek

  • in reply to Quek

    Hi Queck,

    Thank you very much for replying.

    I specified "vn" as a ground net in "Extraction" tab and "0" in ref node.

    I now got different errors, just like these:

    Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
    15.1.4-s005 Fri Nov 20 15:19:16 PST 2015
    -------------------------------------------------------------------------------------------------------------------
    Copyright 2015 Cadence Design Systems,
    Inc.

    WARNING (LBRCXM-624): Warning [input]: Line 6: 'well' statement is ignored in ICT file line.

    WARNING (LBRCXM-624): Warning [input]: Line 7: 'well' statement is ignored in ICT file line.

    WARNING (LBRCXU-240): Syntax error in assura_tech map file /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/tech.def, line 4:
    process_technology

    WARNING (LBRCXU-240): Syntax error in assura_tech map file /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/tech.def, line 5:
    -technology_library_file

    WARNING (LBRCXU-240): Syntax error in assura_tech map file /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/tech.def, line 6:
    -technology_name

    Please help.

    Best regards,

    Marben

  • in reply to Quek

    Hi Quek,

    I can not see any .spi file such as design_pin_xy.spi.

    Also I didn't see any errors during setup.

    I think youre right. I might file a case to the local cadence support.

    Fullscreen query.log Download 
    //  Calibre v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017
//  Calibre Utility Library   v0-2_8-2016-2    Tue Feb 9 23:45:01 PST 2016
//  Litho Libraries v2017.1_34.33  Wed Apr 5 14:22:19 PDT 2017
//
//        Copyright Mentor Graphics Corporation 1996-2017
//                       All Rights Reserved.
//   THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
//      WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
//        OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
//
//  Mentor Graphics software executing under x86-64 Linux
//
//  Running on Linux eda 2.6.32-754.9.1.el6.x86_64 #1 SMP Thu Dec 6 08:02:15 UTC 2018 x86_64 glibc 2.12/NPTL 2.12
//  Processor Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz [062a7]
//  64 bit virtual addressing enabled
//  Running aoi_cal_2017.1_34.33/pkgs/icv/pvt/calibre -query /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb pcd_inv_L -query_input query_cmd
//  Process ID: 11542
//
//  Starting time: Sun Mar 10 05:58:24 2019
//
//  Running on 1 CPU 
//

//  Applying licensing policy...
//  mgc_s license acquired (calibreqdb requested).

//  Licensed Products
//  -----------------
//  Other products:
//  - Query Server

--- CALIBRE::HDB QUERY SERVER --- Sun Mar 10 05:58:24 2019
|-------------------------------- READING PHDB --------------------------------|
################################################################################
--------------------------------------------------------------------------------
-    HDB FOR LAYOUT PRIMARY: "pcd_inv_L" WAS RESTORED FROM SVDB: /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb
-    CROSS REFERENCE WAS RESTORED FROM SVDB: /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/svdb
-    CPU TIME = 1  REAL TIME = 1  LVHEAP = 80/82/82 MALLOC = 55/55/55
--------------------------------------------------------------------------------


--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-----          CALIBRE::HDB QUERY SERVER - EXECUTIVE MODULE                -----
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

INITIATING HDB QUERY SERVER:
--------------
   OK: Ready to serve.
ECHO
   OK: Echo is ON
status
Status 1000
Entries:
0 0 14 Mar 10 05:58:25 2019
Client: 0
View cell: pcd_inv_L
Query instance: (null)
Query cell: pcd_inv_L
Response mode: (direct)
Marker size: 0.25
Maximum vertex count: 4096
Filter distance: 0
Filter layers: (all)
Filter devices: (all)
Filter windows: (none)
Filter cull: X=0 Y=0
Magnify results: 1.0 (default value)
Rotate results: 0.0 (default value)
ReflectX results: Disabled
Translate results: Not Active
PHDB: HIERARCHICAL created with Calibre Version v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017
XDB: HIERARCHICAL created with Calibre Version v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017
END OF RESPONSE
0 0 0 Mar 10 05:58:25 2019
   OK.

## Note that the output directory and file name prefix are consistent
## for all output files. This is an important consideration for running
## QRC with the Calibre input data.
## The QRC input_db -directory_name command argument equates to the
## query output directory (query_output)
## The QRC input_db -run_name command equates to the file name
## prefix (Design) for all query output files.

## CALIBRE QUERY SERVER Script for HCCI

   gds         netprop     number   5
   OK.
   gds         placeprop   number   6
   OK.
   gds         devprop     number   7
   OK.

## Write out GDS Map

   response    file                       query_output/Design.gds.map
   OK.
   gds	       seed property device original
   OK.
   gds         map
   OK.
   response    direct
   OK.

## Write the AGF File (Annotated GDS File)

#  GDS UNITS 1 0.000000001   # only avaialble since Calibre 2006.3 release
   gds         write                      query_output/Design.agf
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## Include trivial pins and empty cells in the layout netlist
## Use only Node Numbers for netlists
## Do not write empty subcircuits for generic devices

   layout      netlist     trivial pins   YES
   OK.
   layout      netlist     empty cells    YES
   OK.
   layout      netlist     names          NONE
   OK.
   layout      netlist     primitive device subckts  NO
   OK.

## Write the Node to Net Name mapping

   layout      nametable   write          query_output/Design.lnn
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## Write a Layout Netlist with Hierarchy and $PIN_XY info

   layout      netlist     hierarchy      AGF
   OK.
   layout      netlist     pin locations  YES
   OK.
   layout      netlist     write          query_output/Design_pin_xy.spi
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## If LVS was run with LVS PUSH DEVICES SEPARATE PROPERTIES YES
## then uncomment nextline to write the separate  properties file
## Query log file will produce NOK pin location message which can be ignored

## layout separated properties write query_output/Design.props

## Write X feference file
## Write the source and layout placement hierarchy files (sph,lph) 

## Default behavior is "ON" for both xref xname layout and schematic,
## which inserts extra "X" for every hierarchy. This is desired for 
## extracted view (qrc deals with it automatically) and Ultrasim 
## stitching flow. For cell level timing analysis flow where verilog 
## does not have extra "X", users can turn on below two options.
#   xref xname layout ON
#   xref xname source OFF

   source       hierarchy   write         query_output/Design.sph

//  Applying licensing policy...
//  mgc_s license acquired (calibreci requested).

//  Licensed Products
//  -----------------
//  Base products running on 1 core:
//  - Calibre Connectivity Interface
//  Other products:
//  - Query Server
   OK.
   layout       hierarchy   write         query_output/Design.lph
   OK.

## Write Cross Reference Files
   net         xref        write          query_output/Design.nxf BOX
   OK.
   instance    xref        write          query_output/Design.ixf
   OK.

## Write the TOP Level and CELL Level Port Tables
   port        table       write          query_output/Design.ports
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.
   port        table cells write          query_output/Design.ports_cells
   ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.

## Generate Device Table for all device info
   response    file 			  query_output/Design.devtab
   OK.
   device      table
   OK.
   response    direct
   OK.

## Report LVS settings
   lvs settings report write                query_output/Design.lvs_settings
   OK.

   terminate
   OK: Terminating.

HDB QUERY SERVER terminated: CPU TIME = 2  REAL TIME = 2  LVHEAP = 1/7/82 MALLOC = 52/52/57

--- CALIBRE::HDB QUERY SERVER COMPLETED - Sun Mar 10 05:58:27 2019
--- TOTAL CPU TIME = 2  REAL TIME = 2  LVHEAP = 1/7/82  MALLOC = 52/52/57  ELAPSED TIME = 3

    Thank you very much for your help again.

    Best regards,

    Marben

  • in reply to Marben

    Hi Marben

    Except for the missing Design_pin_xp.spi file, your query output looks quite ok. Does your Calibre LVS rule deck contain the following cmd?

    MASK SVDB DIRECTORY svdb CCI

    If not, would you please add it, re-run LVS and then re-run query? if it still does not work, you need to work with Mentor AE first to find out why the file is missing.


    Best regards
    Quek

  • in reply to Quek

    Hi Quek,

    My calibre rule deck don't have the command " MASK SVDB DIRECTORY svdb CCI",

    I already added it in my LVS rule deck, but

    same errors exist.

    Can you remote control in my machine using Anydesk or teamviewer?, so that you can assist me.

    Best regards,

    Marben

  • in reply to Marben

    Hi Marben

    It seems that the query log file already tells us that the query did not went well:

       gds         write                      query_output/Design.agf
       ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.
    ...
       layout      nametable   write          query_output/Design.lnn
       ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.
    ...
       layout      netlist     write          query_output/Design_pin_xy.spi
       ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function.


    I made a mistake in the cmd. It should be "MASK SVDB DIRECTORY svdb QUERY CCI". Would you please add the word "QUERY" and try again?

    Best regards
    Quek

  • in reply to Quek

    Hi Quek,

    I already add the "QUERY" in my calibre lvs rule file.

    Fullscreen rule_deck.txt Download 
    #! tvf
namespace import tvf::*

VERBATIM {
MASK SVDB DIRECTORY svdb QUERY CCI
/*
###############################################################################################
#
# GLOBALFOUNDRIES Singapore Pte. Ltd.
#
# File:                 cmos55lpe.lvs.cal
# Description:          Mentor Calibre LVS Runset for CMOS55LPE/RF Process
# Document ID:          EDA-CAD-55N-LV035
# Document Revision:    15
# Author:               Raju Mani
# Date:                 2016-07-31 21:32:43
#
###############################################################################################
# Copyright (c) 2016 GLOBALFOUNDRIES Singapore Pte. Ltd.
###############################################################################################
# This document is confidential and a proprietary product of GLOBALFOUNDRIES Singapore Pte. Ltd.
# Any unauthorized use, reproduction or transfer of this document is strictly prohibited.
###############################################################################################
# Disclaimer:
# -----------
# The information contained herein is confidential and is the property of GLOBALFOUNDRIES and/or
# its licensors.  GLOBALFOUNDRIES reserves all proprietary, design, manufacturing, reproduction,
# use, sales and other rights in the information herein, in its products and services, and to any
# article or process utilizing such information, except to the extent that rights are expressly 
# granted to others.
# This document is for informational purposes only, is current only as of the date of publication
# and is subject to change by GLOBALFOUNDRIES at any time without notice.  While precautions have
# been taken in the preparation of the information herein, it may contain technical inaccuracies,
# omissions and typographical errors. GLOBALFOUNDRIES is under no obligation to update or otherwise
# correct this information.  
# All information contained herein is provided "AS IS."  GLOBALFOUNDRIES makes no representations
# and disclaims all warranties of any kind, express or implied, including without limitation any 
# implied warranties of non-infringement, merchantability or fitness for a particular purpose, 
# with respect to the information contained HEREIN.   
# Terms and conditions applicable to the purchase, quality and use of GLOBALFOUNDRIES' products 
# and services are as set forth in your organization's signed agreement with GLOBALFOUNDRIES or 
# in GLOBALFOUNDRIES' Standard Terms and Conditions of Sale.  Unless otherwise authorized in a 
# signed agreement with GLOBALFOUNDRIES, GLOBALFOUNDRIES' products and services are NOT intended 
# for use in applications such as implantation, life support, or other hazardous uses where 
# malfunction could result in death, bodily injury, or catastrophic property damage.
# GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of 
# GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. Other product or service
# names are for identification purposes only and may be trademarks or service marks of their 
# respective owners.
# � GLOBALFOUNDRIES Inc. 2015. Unless otherwise indicated, all rights reserved. 
# Do not copy or redistribute except as expressly permitted by GLOBALFOUNDRIES.
# 
###############################################################################################
*/
}

VERBATIM {
}


VERBATIM {
//*******************************************************************//
// Header Section                                                    //
//*******************************************************************//

//*******************************************************************//
// SWITCHES FOR THIS CALIBRE LVS DECK                                //
//*******************************************************************//

//*******************************************************************//
// METALLIZATION OPTIONS                                             //
//*******************************************************************//
// You MUST uncomment ONE metallization option.
// For more information see Table 2-7, Preferred Metallization options, in the
// Design Manual.
//
//                  a = # of 1x Thin  layers
//             	  b = # of 2x low-K layers
// a_bc_de_fg:      c = # of 2x FTEOS layers
//                  d = # of 4x low-K layers
//                  e = # of 4x FTEOS layers
//                  f = # of 12x TEOS layers
//                  g = # of 12x FTEOS layers
//
// Top Metal is always LB.
//
//*******************************************************************//
// Uncomment 1 Metallization Option OR use environmental variable BEOL_STACK
//*******************************************************************//
//

//#DEFINE 5_00_01_00_LB    //(M1, M2, M3, M4, M5, EA, LB)
//#DEFINE 6_00_01_00_LB    //(M1, M2, M3, M4, M5, M6, EA, LB)
//#DEFINE 4_02_00_00_LB    //(M1, M2, M3, M4, BA, BB, LB)
//#DEFINE 5_02_00_00_LB    //(M1, M2, M3, M4, M5, BA, BB, LB)
//#DEFINE 6_02_00_00_LB    //(M1, M2, M3, M4, M5, M6, BA, BB, LB)
//#DEFINE 4_00_02_00_LB	   //(M1, M2, M3, M4, EA, EB, LB)
//#DEFINE 5_00_02_00_LB	   //(M1, M2, M3, M4, M5, EA, EB, LB)
//#DEFINE 6_00_02_00_LB	   //(M1, M2, M3, M4, M5, M6, EA, EB, LB)

//RF-Only Metal Options
//#DEFINE 5_00_01_10_LB		//(M1, M2, M3, M4, M5, EA, OI, LB)
//#DEFINE 6_00_01_10_LB		//(M1, M2, M3, M4, M5, M6, EA, OI, LB)
//#DEFINE 5_00_00_10_LB    //(M1, M2, M3, M4, M5, OI, LB)
//#DEFINE 5_01_00_10_LB    //(M1, M2, M3, M4, M5, BA, OI, LB)
//#DEFINE 6_01_00_10_LB    //(M1, M2, M3, M4, M5, M6, BA, OI, LB)

//Alternative Metal Options
//#DEFINE 5_01_00_00_LB		//(M1, M2, M3, M4, M5, BA, LB)
//#DEFINE 6_01_00_00_LB		//(M1, M2, M3, M4, M5, M6, BA, LB)
//#DEFINE 7_01_00_00_LB		//(M1, M2, M3, M4, M5, M6, M7, BA, LB)

}

if [ info exists env(INCLUDE_FILE) ] {
        VERBATIM {INCLUDE $INCLUDE_FILE}
} else {
#        VERBATIM {INCLUDE $TECHDIR/LVS/sample_design.inc.cal}
} 

VERBATIM {
#IFDEF $BEOL_STACK 5_00_00_10_LB  
      #DEFINE 5_00_00_10_LB
#ELSE
#IFDEF $BEOL_STACK 5_00_01_10_LB  
      #DEFINE 5_00_01_10_LB
#ELSE
#IFDEF $BEOL_STACK 6_00_01_10_LB  
      #DEFINE 6_00_01_10_LB
#ELSE
#IFDEF $BEOL_STACK 6_00_02_00_LB  
      #DEFINE 6_00_02_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_00_01_00_LB  
      #DEFINE 5_00_01_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_00_02_00_LB  
      #DEFINE 5_00_02_00_LB
#ELSE
#IFDEF $BEOL_STACK 6_00_01_00_LB  
      #DEFINE 6_00_01_00_LB
#ELSE
#IFDEF $BEOL_STACK 4_00_02_00_LB  
      #DEFINE 4_00_02_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_02_00_00_LB  
      #DEFINE 5_02_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 6_02_00_00_LB  
      #DEFINE 6_02_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 4_02_00_00_LB  
      #DEFINE 4_02_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 5_01_00_10_LB  
      #DEFINE 5_01_00_10_LB
#ELSE
#IFDEF $BEOL_STACK 6_01_00_10_LB  
      #DEFINE 6_01_00_10_LB
#ELSE
#IFDEF $BEOL_STACK 5_01_00_00_LB  
      #DEFINE 5_01_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 6_01_00_00_LB  
      #DEFINE 6_01_00_00_LB
#ELSE
#IFDEF $BEOL_STACK 7_01_00_00_LB  
      #DEFINE 7_01_00_00_LB
#ELSE
       SVRF ERROR "\n\n\n\t  _____NO_VALID_METAL_STACK_OPTION_DEFINED_____  \n\n\n                                   \t\t  Valid options for BEOL_STACK are:               \n\n                                 \t\t\t  5_00_01_10_LB         \n\n                                 \t\t\t  5_00_00_10_LB                       \n\n                                \t\t\t  6_00_02_00_LB                                \n\n                                \t\t\t  5_00_01_00_LB                                \n\n                                \t\t\t  5_00_02_00_LB                                \n\n                                \t\t\t  6_00_01_00_LB                                \n\n                                \t\t\t  4_00_02_00_LB                                \n\n                                \t\t\t  5_02_00_00_LB                                \n\n                                \t\t\t  4_03_00_00_LB                                \n\n                                \t\t\t  6_02_00_00_LB                                \n\n                                \t\t\t  4_02_00_00_LB					\n\n				   \t\t\t  5_01_00_10_LB				\n\n				   \t\t\t  6_01_00_10_LB				\n\n				   \t\t\t  5_01_00_00_LB				\n\n				    \t\t\t  6_01_00_00_LB				\n\n				     \t\t\t  7_01_00_00_LB	                          \n\n  "        
#ENDIF // 7_01_00_00_LB
#ENDIF // 6_01_00_00_LB
#ENDIF // 5_01_00_00_LB
#ENDIF // 6_01_00_10_LB
#ENDIF // 5_01_00_10_LB
#ENDIF // 4_02_00_00_LB
#ENDIF // 6_02_00_00_LB
#ENDIF // 5_02_00_00_LB
#ENDIF // 4_00_02_00_LB
#ENDIF // 6_00_01_00_LB
#ENDIF // 5_00_02_00_LB
#ENDIF // 5_00_01_00_LB
#ENDIF // 6_00_02_00_LB
#ENDIF // 6_00_01_10_LB
#ENDIF // 5_00_01_10_LB
#ENDIF // 5_00_00_10_LB
 }

VERBATIM {
//*******************************************************************//

//*******************************************************************//
// SWITCHES - see documentation for description and proper usage     //
//*******************************************************************//


////////////////////////////////////////////////////////////////////
//                     Custom Switches                            //
////////////////////////////////////////////////////////////////////
// ***NOTE: Refer to the Calibre LVS release notes to learn how to
//          set these new environmental variables.***
////////////////////////////////////////////////////////////////////
//*******************************************************************//
//
//
// This option is used to not compare device properties.
// Uncomment this option if you do not want property comparison. 
// Be careful using this.
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $NO_TRACE_PROPERTY = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE NO_TRACE_PROPERTY
//
#IFDEF $NO_TRACE_PROPERTY TRUE
  #DEFINE NO_TRACE_PROPERTY
#ENDIF

// This option is used to NOT compare FET nf property.
// Use this option if you do not want nf property comparison. 
// Be carefull using this.
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $CHECK_NUMBER_OF_FINGERS = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE IGNORE_NF_PARAM
//

#IFDEF $CHECK_NUMBER_OF_FINGERS FALSE
	#DEFINE IGNORE_NF_PARAM
#ENDIF

//*******************************************************************//
// This option is used to compare TIEDOWN DIODES tdndsx/tdpdnw 
// Area and Perimeter properties.
// Use this option if you want A and perim property comparison. .
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $CHECK_TIEDOWN_PARAM = TRUE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE CHECK_TIEDOWN_PARAM
//

#IFDEF $CHECK_TIEDOWN_PARAM TRUE
	#DEFINE CHECK_TIEDOWN_PARAM
#ENDIF

//
//*******************************************************************//
// This option is used not to compare pccrit property of FETs or not.
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $IGNORE_PCCRIT_PARAM = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
// Hardcoded to TRUE because pccrit is not supported in the technology.
#DEFINE IGNORE_PCCRIT_PARAM
//
#IFDEF $IGNORE_PCCRIT_PARAM  TRUE
   #DEFINE IGNORE_PCCRIT_PARAM
#ENDIF
		
//*******************************************************************//
//
// To run PEX, define "PEX_RUN"
// To run LVS, do not define "PEX_RUN" 
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $PEX_RUN = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE PEX_RUN
// 
#IFDEF $PEX_RUN TRUE
  #DEFINE PEX_RUN
  #IFDEF $CORNERROUNDING TRUE
    #DEFINE CORNERROUNDING    // corner rounding is only valid when PEX_RUN is set to TRUE
  #ENDIF
#ENDIF	
	
//*******************************************************************//
//
// To run ERC, define "ERC_RUN"
//
// $ERC_RUN = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//#DEFINE ERC_RUN
//
#IFDEF $ERC_RUN TRUE
  #DEFINE ERC_RUN
#ENDIF

//*******************************************************************//
//
// Series MOS reduction is not permitted by Default
// Uncomment the switch below if user wants to reduce sreies MOS devices
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $REDUCE_SERIES_MOS = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
//#DEFINE REDUCE_SERIES_MOS
// 
#IFDEF $REDUCE_SERIES_MOS TRUE
  #DEFINE REDUCE_SERIES_MOS
#ENDIF

//*******************************************************************//
//
// Split gate MOS reduction is not permitted by Default
// Uncomment the switch below if user wants to reduce sreies MOS devices
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $REDUCE_SPLIT_GATES = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
//#DEFINE REDUCE_SPLIT_GATES
// 

#IFDEF $REDUCE_SPLIT_GATES TRUE
  #DEFINE REDUCE_SPLIT_GATES
#ENDIF

//*******************************************************************//
//
// LVS recognize RX FILL as RX drawing by default.
// Uncomment the switch below if user wants to exclude RX FILL as drawing
//
// To enable/disable this switch please use the following 
// environmental variable:
//
// $EXCLUDE_RX_FILL = TRUE/FALSE
//
//======================================
// If environmental variables are being
// used, do NOT edit the next lines!
//======================================
//
//#DEFINE EXCLUDE_RX_FILL
// 

#IFDEF $EXCLUDE_RX_FILL TRUE
  #DEFINE EXCLUDE_RX_FILL
#ENDIF

//*******************************************************************//
//
// By default,LVS use 2K high-Rs p+ poly resistor
// To define 1K p+ poly resistor,please use the following environmental variable:
//
//    $POLY_HIGH_RES =  [1K || 2K]
//
//    e.g.
//    setenv POLY_HIGH_RES 1K # [1K || 2K]
//
//========================================================================================================//
// If environmental variables are being used, do NOT edit the next lines!                                 //
//========================================================================================================//
// #DEFINE POLY_HIGH_RES_1K // Uncomment this line to extract 1K p+ poly resistor
//
#IFDEF $POLY_HIGH_RES 1K
   #DEFINE POLY_HIGH_RES_1K
#ENDIF // $POLY_HIGH_RES
//

//*******************************************************************//


//*******************************************************************//
// Include files                                                     //
//*******************************************************************//
// General calibre tool options which users are required to set have
// been move to design include file, please use $INCLUDE_FILE to locate
// user include file, by default sample_design.inc.cal will be included.
// INCLUDE $TECHDIR/LVS/sample_design.inc.cal
#IFDEF $TECHDIR
#ENDIF
   
}

VERBATIM {
//*******************************************************************//
// Description Section                                               //
//*******************************************************************//

//INCLUDE $TECHDIR/LVS/Include/cmos55lpe.extract.cal_ind
//INCLUDE $TECHDIR/LVS/Include/cmos55lpe.layers.cal_ind
INCLUDE $TECHDIR/LVS/Include/cmos55lpe.extract.cal
INCLUDE $TECHDIR/LVS/Include/cmos55lpe.compare.cal
INCLUDE $TECHDIR/LVS/Include/cmos55lpe.layers.cal

LVS FILTER D(diodepwtw) OPEN
LVS FILTER D(diodetwx) OPEN
LVS FILTER D(diodenwx) OPEN
LVS FILTER D(diodenx) OPEN
LVS FILTER D(diodepnw) OPEN
LVS FILTER D(diodedgnx) OPEN
LVS FILTER D(diodedgpnw) OPEN
LVS FILTER D(diodehvpwtw) OPEN
LVS FILTER D(diodeisotwx) OPEN
	
LVS SOFTCHK nband CONTACT
LVS SOFTCHK psub CONTACT
 
LVS SOFTCHK nw_no_n3 CONTACT
LVS SOFTCHK nw_n3_t3 CONTACT

#IFDEF ERC_RUN
   ERC SELECT CHECK FLOATING_CHKs
#ENDIF
ERC RESULTS DATABASE "./ERC_results.asc"
ERC SUMMARY REPORT "./ERC_results.rep"

//*******************************************************************//
// SET Series & Parallel STATEMENTS                                  //
//*******************************************************************//

#IFNDEF REDUCE_SPLIT_GATES
   LVS REDUCE SPLIT GATES NO
#ENDIF

LVS REDUCE SEMI SERIES MOS             NO  //YES
LVS REDUCE SERIES MOS                  NO  //YES

LVS REDUCE PARALLEL BIPOLAR            YES //YES
LVS REDUCE PARALLEL CAPACITORS         YES //YES
LVS REDUCE PARALLEL DIODES             YES //YES
LVS REDUCE PARALLEL MOS                YES //YES
LVS REDUCE PARALLEL RESISTORS          YES //YES

LVS REDUCE SERIES CAPACITORS           YES //YES
LVS REDUCE SERIES RESISTORS            YES //YES

LVS REDUCE D(tdpdnw) PARALLEL YES 
LVS REDUCE D(tdndsx) PARALLEL YES
LVS REDUCE D(tddgpdnw) PARALLEL YES 
LVS REDUCE D(tddgndsx) PARALLEL YES


//*******************************************************************//
// END SET REDUCE STATEMENTS                                         //
//*******************************************************************//


//*******************************************************************//
// Set TRACE Tolerances - Do Not Change                              //
//*******************************************************************//

VARIABLE trace_hg 2.5e-9
VARIABLE trace_int 0.5
VARIABLE trace_area 1e-15

//*******************************************************************//
// End of Header Section                                             //
//*******************************************************************//

//********************************************************************//
// END OF FILE                                                       //
//********************************************************************//

}

    But same error exist.

    Please help.

    Best regards,

    Marben

  • in reply to Marben

    Hi Marben

    I think there might be another "MASK SVDB DIRECTORY ..." cmd in the rule deck that has incorrect options and had overwritten your cmd. You can do a search in the rule deck directory:

    terminal> egrep -ir "mask svdb directory" /your-path/yourRuleDeckDir

    If you still cannot find the issue, it is best if you file a case to Mentor support so that they can first help to resolve the missing query files issue. I think it is most probably just a setup issue but it is difficult to debug without access to it.


    Best regards
    Quek

  • in reply to Quek

    Hi Quek,

    Here is the result of my egrep.

    I think they are all in comment.

    Best regards,

    Marben

  • in reply to Marben

    Hi Marben

    If you check Calibre LVS log file and report file, are you able to find any "MASK SVDB DIRECTORY" cmds?

    After adding cmd in Calibre LVS deck, did you remember to re-run LVS?


    Thanks
    Quek

  • in reply to Quek

    Hi Quek,

    I do not know what is the filename of my LVS log file,

    what is the extension name of calibre lvs log file?

    Yes, Aftre adding cmd in calibre lvs deck I rerun LVS then query.

    I can not find "MASK SVDB DIRECTORY" in my LVS report file.

    Fullscreen report_file.txt Download 
    

                  ##################################################
                  ##                                              ##
                  ##         C A L I B R E    S Y S T E M         ##
                  ##                                              ##
                  ##             L V S   R E P O R T              ##
                  ##                                              ##
                  ##################################################



REPORT FILE NAME:         pcd_inv_L.lvs.report
LAYOUT NAME:              svdb/pcd_inv_L.sp ('pcd_inv_L')
SOURCE NAME:              /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/pcd_inv_L.src.net ('pcd_inv_L')
RULE FILE:                /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area/_cmos55lpe.lvs_ref.cal_
CREATION TIME:            Sun Mar 10 22:41:14 2019
CURRENT DIRECTORY:        /home/marben/GF55/GF_stuff/Components/cmos10lpe_CDS_oa_dl064_15_20170731/DRC_LVS_Run_Area
USER NAME:                marben
CALIBRE VERSION:          v2017.1_34.33    Wed Apr 5 14:22:19 PDT 2017



                               OVERALL COMPARISON RESULTS



                         #       ###################       _   _   
                        #        #                 #       *   *   
                   #   #         #     CORRECT     #         |     
                    # #          #                 #       \___/  
                     #           ###################               




**************************************************************************************************************
                                      CELL  SUMMARY
**************************************************************************************************************

  Result         Layout                        Source
  -----------    -----------                   --------------
  CORRECT        pcd_inv_L                     pcd_inv_L



**************************************************************************************************************
                                      LVS PARAMETERS
**************************************************************************************************************


o LVS Setup:

   // LVS COMPONENT TYPE PROPERTY
   // LVS COMPONENT SUBTYPE PROPERTY
   // LVS PIN NAME PROPERTY
   LVS POWER NAME                         "VDD?" "DVDD?" "VDDC?" "VNWP?" "VDDP?" "VNW?" "VDD:P?" "VCC?" "VCC:P?" "WDPWRA?"
                                          "WDPWRB?" "WDPWR?"
   LVS GROUND NAME                        "VSS?" "GND?" "DVSS?" "SUB?" "sub"
   LVS CELL SUPPLY                        NO
   LVS RECOGNIZE GATES                    ALL
   LVS IGNORE PORTS                       NO
   LVS CHECK PORT NAMES                   NO
   LVS IGNORE TRIVIAL NAMED PORTS         NO
   LVS BUILTIN DEVICE PIN SWAP            NO
   LVS ALL CAPACITOR PINS SWAPPABLE       NO
   LVS DISCARD PINS BY DEVICE             NO
   LVS SOFT SUBSTRATE PINS                NO
   LVS INJECT LOGIC                       YES
   LVS EXPAND UNBALANCED CELLS            YES
   LVS FLATTEN INSIDE CELL                NO
   LVS EXPAND SEED PROMOTIONS             NO
   LVS PRESERVE PARAMETERIZED CELLS       NO
   LVS GLOBALS ARE PORTS                  YES
   LVS REVERSE WL                         NO
   LVS SPICE PREFER PINS                  NO
   LVS SPICE SLASH IS SPACE               YES
   LVS SPICE ALLOW FLOATING PINS          YES
   // LVS SPICE ALLOW INLINE PARAMETERS     
   LVS SPICE ALLOW UNQUOTED STRINGS       NO
   LVS SPICE CONDITIONAL LDD              NO
   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
   LVS SPICE IMPLIED MOS AREA             NO
   // LVS SPICE MULTIPLIER NAME
   LVS SPICE OVERRIDE GLOBALS             NO
   LVS SPICE REDEFINE PARAM               NO
   LVS SPICE REPLICATE DEVICES            YES
   LVS SPICE SCALE X PARAMETERS           NO
   LVS SPICE STRICT WL                    NO
   // LVS SPICE OPTION
   LVS STRICT SUBTYPES                    NO
   LVS EXACT SUBTYPES                     NO
   LAYOUT CASE                            NO
   SOURCE CASE                            NO
   LVS COMPARE CASE                       NO
   LVS DOWNCASE DEVICE                    NO
   LVS REPORT MAXIMUM                     50
   LVS PROPERTY RESOLUTION MAXIMUM        32
   // LVS SIGNATURE MAXIMUM
   // LVS FILTER UNUSED OPTION
   // LVS REPORT OPTION
   LVS REPORT UNITS                       YES
   // LVS NON USER NAME PORT
   // LVS NON USER NAME NET
   // LVS NON USER NAME INSTANCE
   // LVS IGNORE DEVICE PIN

   // Reduction

   LVS REDUCE SERIES MOS                  NO
   LVS REDUCE PARALLEL MOS                YES
   LVS REDUCE SEMI SERIES MOS             NO
   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 0 ]
   LVS REDUCE PARALLEL BIPOLAR            YES
   LVS REDUCE SERIES CAPACITORS           YES
   LVS REDUCE PARALLEL CAPACITORS         YES
   LVS REDUCE SERIES RESISTORS            YES
   LVS REDUCE PARALLEL RESISTORS          YES
   LVS REDUCE PARALLEL DIODES             YES

   LVS REDUCE  MN(nfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MN(nfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  nfettw  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  nfettw  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MP(pfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MP(pfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(lvtnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(lvtnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  lvtnfettw  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  lvtnfettw  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(lvtpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(lvtpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(hvtnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(hvtnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  hvtnfettw  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  hvtnfettw  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(hvtpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(hvtpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgvnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgvnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  dgvnfettw  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  dgvnfettw  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgvpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgvpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  dgnfettw  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  dgnfettw  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgxnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgxnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  dgxnfettw  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  dgxnfettw  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgxpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgxpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MN(natnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MN(natnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MN(natdgnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MN(natdgnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  MN(natdgxnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MN(natdgxnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  ME(ednfet)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  ME(edpfet)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  M(isoednfet)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  M(isoedpfet)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  M(isosednfet)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  Q(ngrvpnp)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 mSwitch 0 ]
   LVS REDUCE  Q(vpnp)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 mSwitch 0 ]
   LVS REDUCE  Q(vnpn)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 ]
   LVS REDUCE  R(opppcres)  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  R(opppcres)  SERIES POS NEG [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  R(opppcres_1k)  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  R(opppcres_1k)  SERIES POS NEG [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  R(opndres)  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  R(opndres)  SERIES POS NEG [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  R(nwres)  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  R(nwres)  SERIES POS NEG [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  R(lvsres)  PARALLEL
   LVS REDUCE  R(rm1)  PARALLEL
   LVS REDUCE  R(rm2)  PARALLEL
   LVS REDUCE  R(rm3)  PARALLEL
   LVS REDUCE  R(rm4)  PARALLEL
   LVS REDUCE  R(rm5)  PARALLEL
   LVS REDUCE  R(rmea)  PARALLEL
   LVS REDUCE  subc  PARALLEL
   LVS REDUCE  subc  SERIES SUBCON sub NO
   LVS REDUCE  C(pcap)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  C(pcap)  SERIES POS NEG NO
   LVS REDUCE  C(dgpcap)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  C(dgpcap)  SERIES POS NEG NO
   LVS REDUCE  C(ncap)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  C(ncap)  SERIES POS NEG NO
   LVS REDUCE  C(dgncap)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  C(dgncap)  SERIES POS NEG NO
   LVS REDUCE  C(vncap)  PARALLEL NO
   LVS REDUCE  C(vncap)  SERIES POS NEG NO
   LVS REDUCE  C(apmom)  PARALLEL NO
   LVS REDUCE  C(apmom)  SERIES POS NEG NO
   LVS REDUCE  C(vncap_rf)  PARALLEL NO
   LVS REDUCE  C(vncap_rf)  SERIES POS NEG NO
   LVS REDUCE  C(apmom_rf)  PARALLEL NO
   LVS REDUCE  C(apmom_rf)  SERIES POS NEG NO
   LVS REDUCE  C(MOM20_rf)  PARALLEL NO
   LVS REDUCE  C(MOM24_rf)  PARALLEL NO
   LVS REDUCE  C(MOM25_rf)  PARALLEL NO
   LVS REDUCE  C(MOM20_rf)  SERIES POS NEG NO
   LVS REDUCE  C(MOM24_rf)  SERIES POS NEG NO
   LVS REDUCE  C(MOM25_rf)  SERIES POS NEG NO
   LVS REDUCE  sblkndres  PARALLEL NO
   LVS REDUCE  sblkpdres  PARALLEL NO
   LVS REDUCE  D(esdndsx)  PARALLEL
   LVS REDUCE  Q(esdvpnp)  PARALLEL [ TOLERANCE nf 0 A 0 ]
   LVS REDUCE  Q(esdvnpn)  PARALLEL [ TOLERANCE nf 0 A 0 ]
   LVS REDUCE  M(srpubpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpubpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpdbnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpdbnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpgbnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpgbnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpucpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpucpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpdcnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpdcnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpgcnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpgcnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpudpfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpudpfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpddnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpddnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpgdnfet)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(srpgdnfet)  SERIES S D [ TOLERANCE l 0 ]
   LVS REDUCE  C(ncap_rf)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  C(ncap_rf)  SERIES POS NEG NO
   LVS REDUCE  C(dgncap_rf)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  C(dgncap_rf)  SERIES POS NEG NO
   LVS REDUCE  pcap_rf  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  pcap_rf  SERIES G D NO
   LVS REDUCE  dgpcap_rf  PARALLEL [ TOLERANCE nf 0 w 0 l 0 nrep 0 composite 0 mSwitch 0 ]
   LVS REDUCE  dgpcap_rf  SERIES G D NO
   LVS REDUCE  MN(nfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  nfettw_rf  PARALLEL NO
   LVS REDUCE  MP(pfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(lvtnfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  lvtnfettw_rf  PARALLEL NO
   LVS REDUCE  M(lvtpfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  M(hvtnfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  hvtnfettw_rf  PARALLEL NO
   LVS REDUCE  M(hvtpfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgvnfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  dgvnfettw_rf  PARALLEL NO
   LVS REDUCE  MD(dgvpfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgxnfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  dgxnfettw_rf  PARALLEL NO
   LVS REDUCE  MD(dgxpfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  MD(dgnfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  dgnfettw_rf  PARALLEL NO
   LVS REDUCE  MD(dgpfet_rf)  PARALLEL [ TOLERANCE l 0 ]
   LVS REDUCE  ME(ednfet_rf)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  ME(edpfet_rf)  PARALLEL [ TOLERANCE l 0 w 0 ]
   LVS REDUCE  C(mimcap_alt)  PARALLEL [ TOLERANCE w 0 l 0 ]
   LVS REDUCE  C(mimcap_alt_bb)  PARALLEL [ TOLERANCE w 0 l 0 ]
   LVS REDUCE  C(mimcap_alt)  SERIES POS NEG NO
   LVS REDUCE  C(mimcap_alt_bb)  SERIES POS NEG NO
   LVS REDUCE  D(esdndsx_rf)  PARALLEL
   LVS REDUCE  Q(esdvpnp_rf)  PARALLEL [ TOLERANCE nf 0 A 0 ]
   LVS REDUCE  Q(esdvnpn_rf)  PARALLEL [ TOLERANCE nf 0 A 0 ]
   LVS REDUCE  R(oprppres)  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  R(oprppres)  SERIES POS NEG [ TOLERANCE w 0 l 0 s 0 pbar 0 ]
   LVS REDUCE  npolyf_s  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  npolyf_u  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  ppolyf_s  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  nplus_s  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  pplus_s  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  pplus_u  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  nwella  PARALLEL [ TOLERANCE w 0 l 0 s 0 ]
   LVS REDUCE  npolyf_s  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  npolyf_u  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  ppolyf_s  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  nplus_s  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  pplus_s  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  pplus_u  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  nwella  SERIES PLUS MINUS [ TOLERANCE w 0 l 0 pbar 0 ]
   LVS REDUCE  MN(nmos_5p0_asym)  PARALLEL [ TOLERANCE l 0 w 0 nf 0 ]
   LVS REDUCE  MP(pmos_5p0_asym)  PARALLEL [ TOLERANCE l 0 w 0 nf 0 ]
   LVS REDUCE  D(tdpdnw)  PARALLEL
   LVS REDUCE  D(tdndsx)  PARALLEL
   LVS REDUCE  D(tddgpdnw)  PARALLEL
   LVS REDUCE  D(tddgndsx)  PARALLEL
   LVS REDUCTION PRIORITY                 PARALLEL
   
   LVS SHORT EQUIVALENT NODES             NO

   // Filter

   LVS FILTER  D(diodepwtw)  OPEN
   LVS FILTER  D(diodetwx)  OPEN
   LVS FILTER  D(diodenwx)  OPEN
   LVS FILTER  D(diodenx)  OPEN
   LVS FILTER  D(diodepnw)  OPEN
   LVS FILTER  D(diodedgnx)  OPEN
   LVS FILTER  D(diodedgpnw)  OPEN
   LVS FILTER  D(diodehvpwtw)  OPEN
   LVS FILTER  D(diodeisotwx)  OPEN

   // Trace Property

   TRACE PROPERTY  mn(nfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(nfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nfettw  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nfettw  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mp(pfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mp(pfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  lvtnfettw  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  lvtnfettw  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  hvtnfettw  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  hvtnfettw  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgvnfettw  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgvnfettw  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgnfettw  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgnfettw  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgxnfettw  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgxnfettw  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(natnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(natnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(natdgnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(natdgnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(natdgxnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(natdgxnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(ednfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(ednfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(edpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(edpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(isoednfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(isoednfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(isoedpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(isoedpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(isosednfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(isosednfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(ngrvpnp)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(ngrvpnp)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(ngrvpnp)  nf nf 0
   TRACE PROPERTY  q(ngrvpnp)  nrep nrep 0
   TRACE PROPERTY  q(ngrvpnp)  m m 0
   TRACE PROPERTY  q(vpnp)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(vpnp)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(vpnp)  nf nf 0
   TRACE PROPERTY  q(vpnp)  nrep nrep 0
   TRACE PROPERTY  q(vpnp)  m m 0
   TRACE PROPERTY  q(vnpn)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(vnpn)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  q(vnpn)  nf nf 0
   TRACE PROPERTY  q(vnpn)  nrep nrep 0
   TRACE PROPERTY  q(vnpn)  m m 0
   TRACE PROPERTY  r(opppcres)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres)  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres)  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres_1k)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres_1k)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres_1k)  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opppcres_1k)  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opndres)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opndres)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opndres)  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(opndres)  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(nwres)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(nwres)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(nwres)  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(nwres)  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm1)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm1)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm2)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm2)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm3)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm3)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm4)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm4)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm5)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rm5)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rmea)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(rmea)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(pcap)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(pcap)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  c(pcap)  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(pcap)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(pcap)  m m 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgpcap)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(dgpcap)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgpcap)  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgpcap)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(dgpcap)  m m 0.5 ABSOLUTE
   TRACE PROPERTY  c(ncap)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(ncap)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  c(ncap)  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(ncap)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(ncap)  m m 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgncap)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(dgncap)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgncap)  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgncap)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(dgncap)  m m 0.5 ABSOLUTE
   TRACE PROPERTY  c(vncap)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(vncap)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(vncap)  botlev botlev 0.5
   TRACE PROPERTY  c(vncap)  toplev toplev 0.5
   TRACE PROPERTY  c(apmom)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(apmom)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(apmom)  botlev botlev 0.5
   TRACE PROPERTY  c(apmom)  toplev toplev 0.5
   TRACE PROPERTY  c(vncap_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(vncap_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(vncap_rf)  botlev botlev 0.5
   TRACE PROPERTY  c(vncap_rf)  toplev toplev 0.5
   TRACE PROPERTY  c(apmom_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(apmom_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(apmom_rf)  botlev botlev 0.5
   TRACE PROPERTY  c(apmom_rf)  toplev toplev 0.5
   TRACE PROPERTY  c(mom20_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mom20_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mom20_rf)  botlev botlev 0.5
   TRACE PROPERTY  c(mom20_rf)  toplev toplev 0.5
   TRACE PROPERTY  c(mom20_rf)  shield_option shield_option 0
   TRACE PROPERTY  c(mom24_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mom24_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mom24_rf)  botlev botlev 0.5
   TRACE PROPERTY  c(mom24_rf)  toplev toplev 0.5
   TRACE PROPERTY  c(mom24_rf)  shield_option shield_option 0
   TRACE PROPERTY  c(mom25_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mom25_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mom25_rf)  botlev botlev 0.5
   TRACE PROPERTY  c(mom25_rf)  toplev toplev 0.5
   TRACE PROPERTY  c(mom25_rf)  shield_option shield_option 0
   TRACE PROPERTY  sblkndres  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  sblkndres  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  sblkpdres  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  sblkpdres  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  d(esdndsx)  a a 1
   TRACE PROPERTY  d(esdndsx)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  d(esdndsx)  perim perim 1
   TRACE PROPERTY  q(esdvpnp)  a a 1
   TRACE PROPERTY  q(esdvpnp)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  q(esdvnpn)  a a 1
   TRACE PROPERTY  q(esdvnpn)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  esdscr_dw  nf nf 0
   TRACE PROPERTY  esdscr_dw  ntds ntds 0
   TRACE PROPERTY  esdscr_dw  areapd areapd 1
   TRACE PROPERTY  esdscr_dw  perimpd perimpd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_dw  areanw areanw 1
   TRACE PROPERTY  esdscr_dw  perimnw perimnw 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_dw  areand areand 1
   TRACE PROPERTY  esdscr_dw  perimnd perimnd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw  nf nf 0
   TRACE PROPERTY  esdscr_tw  ntds ntds 0
   TRACE PROPERTY  esdscr_tw  areapd areapd 1
   TRACE PROPERTY  esdscr_tw  perimpd perimpd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw  areanw areanw 1
   TRACE PROPERTY  esdscr_tw  perimnw perimnw 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw  areand areand 1
   TRACE PROPERTY  esdscr_tw  perimnd perimnd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw  areapw areapw 1
   TRACE PROPERTY  esdscr_tw  perimpw perimpw 1e-07 ABSOLUTE
   TRACE PROPERTY  m(srpubpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpubpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpdbnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpdbnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpgbnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpgbnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpucpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpucpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpdcnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpdcnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpgcnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpgcnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpudpfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpudpfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpddnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpddnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpgdnfet)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(srpgdnfet)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  symindp  din din 0
   TRACE PROPERTY  symindp  width width 0
   TRACE PROPERTY  symindp  n n 0
   TRACE PROPERTY  symindp  ct ct 0
   TRACE PROPERTY  symindp  shield shield 0
   TRACE PROPERTY  c(ncap_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(ncap_rf)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  c(ncap_rf)  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(ncap_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(ncap_rf)  m m 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgncap_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(dgncap_rf)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgncap_rf)  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(dgncap_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(dgncap_rf)  m m 0.5 ABSOLUTE
   TRACE PROPERTY  pcap_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pcap_rf  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  pcap_rf  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  pcap_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pcap_rf  m m 0.5 ABSOLUTE
   TRACE PROPERTY  dgpcap_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgpcap_rf  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  dgpcap_rf  nrep nrep 0.5 ABSOLUTE
   TRACE PROPERTY  dgpcap_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgpcap_rf  m m 0.5 ABSOLUTE
   TRACE PROPERTY  mn(nfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(nfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nfettw_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nfettw_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mp(pfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mp(pfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtnfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtnfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  lvtnfettw_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  lvtnfettw_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtpfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(lvtpfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtnfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtnfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  hvtnfettw_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  hvtnfettw_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtpfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  m(hvtpfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvnfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvnfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgvnfettw_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgvnfettw_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvpfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgvpfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxnfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxnfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgxnfettw_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgxnfettw_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxpfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgxpfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgnfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgnfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgnfettw_rf  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  dgnfettw_rf  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgpfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  md(dgpfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(ednfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(ednfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(edpfet_rf)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  me(edpfet_rf)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt)  lrep lrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt)  wrep wrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt_bb)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt_bb)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt_bb)  lrep lrep 0.5 ABSOLUTE
   TRACE PROPERTY  c(mimcap_alt_bb)  wrep wrep 0.5 ABSOLUTE
   TRACE PROPERTY  indp  n n 0
   TRACE PROPERTY  indp  din din 0
   TRACE PROPERTY  indp  width width 0
   TRACE PROPERTY  indp  shield shield 0
   TRACE PROPERTY  d(esdndsx_rf)  a a 1
   TRACE PROPERTY  d(esdndsx_rf)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  d(esdndsx_rf)  perim perim 1
   TRACE PROPERTY  q(esdvpnp_rf)  a a 1
   TRACE PROPERTY  q(esdvpnp_rf)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  q(esdvnpn_rf)  a a 1
   TRACE PROPERTY  q(esdvnpn_rf)  nf nf 0.5 ABSOLUTE
   TRACE PROPERTY  r(oprppres)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(oprppres)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(oprppres)  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  r(oprppres)  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  bondpad  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  bondpad  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  bondpad  bp bp 0
   TRACE PROPERTY  bondpad  rect rect 0
   TRACE PROPERTY  esdscr_dw_rf  nf nf 0
   TRACE PROPERTY  esdscr_dw_rf  ntds ntds 0
   TRACE PROPERTY  esdscr_dw_rf  areapd areapd 1
   TRACE PROPERTY  esdscr_dw_rf  perimpd perimpd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_dw_rf  areanw areanw 1
   TRACE PROPERTY  esdscr_dw_rf  perimnw perimnw 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_dw_rf  areand areand 1
   TRACE PROPERTY  esdscr_dw_rf  perimnd perimnd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw_rf  nf nf 0
   TRACE PROPERTY  esdscr_tw_rf  ntds ntds 0
   TRACE PROPERTY  esdscr_tw_rf  areapd areapd 1
   TRACE PROPERTY  esdscr_tw_rf  perimpd perimpd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw_rf  areanw areanw 1
   TRACE PROPERTY  esdscr_tw_rf  perimnw perimnw 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw_rf  areand areand 1
   TRACE PROPERTY  esdscr_tw_rf  perimnd perimnd 1e-07 ABSOLUTE
   TRACE PROPERTY  esdscr_tw_rf  areapw areapw 1
   TRACE PROPERTY  esdscr_tw_rf  perimpw perimpw 1e-07 ABSOLUTE
   TRACE PROPERTY  mn(nmos_5p0_asym)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mn(nmos_5p0_asym)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mp(pmos_5p0_asym)  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  mp(pmos_5p0_asym)  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_s  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_s  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_s  m m 0
   TRACE PROPERTY  npolyf_s  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_s  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_u  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_u  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_u  m m 0
   TRACE PROPERTY  npolyf_u  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  npolyf_u  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  ppolyf_s  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  ppolyf_s  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  ppolyf_s  m m 0
   TRACE PROPERTY  ppolyf_s  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  ppolyf_s  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nplus_s  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nplus_s  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nplus_s  m m 0
   TRACE PROPERTY  nplus_s  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nplus_s  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_s  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_s  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_s  m m 0
   TRACE PROPERTY  pplus_s  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_s  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_u  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_u  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_u  m m 0
   TRACE PROPERTY  pplus_u  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  pplus_u  pbar pbar 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nwella  l l 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nwella  w w 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nwella  m m 0
   TRACE PROPERTY  nwella  s s 2.5e-09 ABSOLUTE
   TRACE PROPERTY  nwella  pbar pbar 2.5e-09 ABSOLUTE



                   CELL COMPARISON RESULTS ( TOP LEVEL )



                         #       ###################       _   _   
                        #        #                 #       *   *   
                   #   #         #     CORRECT     #         |     
                    # #          #                 #       \___/  
                     #           ###################               



LAYOUT CELL NAME:         pcd_inv_L
SOURCE CELL NAME:         pcd_inv_L

--------------------------------------------------------------------------------------------------------------

NUMBERS OF OBJECTS
------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              5         5

 Nets:               5         5

 Instances:          2         2         MD (4 pins)
                ------    ------
 Total Inst:         2         2



**************************************************************************************************************
                               INFORMATION AND WARNINGS
**************************************************************************************************************


                  Matched    Matched    Unmatched    Unmatched    Component
                   Layout     Source       Layout       Source    Type
                  -------    -------    ---------    ---------    ---------
   Ports:               5          5            0            0

   Nets:                5          5            0            0

   Instances:           1          1            0            0    MD(DGNFET)
                        1          1            0            0    MD(DGPFET)
                  -------    -------    ---------    ---------
   Total Inst:          2          2            0            0


o Layout Names That Are Missing In The Source:

   Ports:        VN:
   Nets:         VN:


o Initial Correspondence Points:

   Ports:        SB VP A Y


**************************************************************************************************************
                                         SUMMARY
**************************************************************************************************************

Total CPU Time:      1 sec
Total Elapsed Time:  1 sec

    Best regards,

    Marben

  • in reply to Marben

    Hi Marben

    I think it would be best if you contact Mentor support centre to sort out the Calibre LVS and query issues first.


    Best regards
    Quek

Reply Children
  • in reply to Quek

    Hi Quek,

    Yes, I will contact Mentor support.

    Thank you very much for your help.

    Best regards,

    Marben

  • in reply to Quek

    Hi Quek,

    I asked in Mentor support.

    The error "ERROR(130): Incorrect MASK SVDB DIRECTORY options for this function." is gone affter

    adding "MASK SVDB DIRECTORY "svdb" QUERY CCI" to my LVS rule deck.

    And click the checkbox "Generate Calibre Connectivity Interface data"  in calibre Outputs tab.

    Then I click Run LVS and run query.

    I now have an spi file generated in my query output folder.

    But, still calibre qrc runs failed.

    Please help.

    Best regards,

    Marben

    Fullscreen 1651.qrc.r1.log Download 
    
  Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
15.1.4-s005 Fri Nov 20 15:19:16 PST 2015
-------------------------------------------------------------------------------------------------------------------
                                    Copyright 2015 Cadence Design Systems,
Inc.

WARNING (LBRCXM-624): Warning [input]: Line 6: 'well' statement is ignored in ICT file line.

WARNING (LBRCXM-624): Warning [input]: Line 7: 'well' statement is ignored in ICT file line.

INFO (LBRCXM-630): Starting extraction: Mon Mar 11 12:33:43 2019


ERROR (AGDPRP-31003): can't open /home/marben/query_output/query_output/r1_pin_xy.spi

INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
 agdsPrep -V -rundir /home/marben/query_output/query_output -outdir /home/marben/query_output/query_output/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile

Forking: agdsPrep -V -rundir /home/marben/query_output/query_output -outdir /home/marben/query_output/query_output/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile
ERROR (LBRCXM-633): Bad return status from RCX script generator. Status 256

INFO (LBRCXM-709): *****  Quantus QRC terminated abnormally  *****

  • in reply to Quek

    Hi Quek,
    I copied Design_pin_xy.spi to r1_pin_xy.spi,
    The error "ERROR (AGDPRP-31003): can't open /home/marben/query_output/query_output/r1_pin_xy.spi" is gone.
    Here is now my error.
    ERROR (AGDPRP-31040): output_setup -net_name_space "SCHEMATIC" is not supported with extract-only data. Specify output_setup -net_name_space "LAYOUT" instead.

    Please help.
    Best regards,
    Marben

    Fullscreen 3771.qrc.r1.log Download 
    
  Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
15.1.4-s005 Fri Nov 20 15:19:16 PST 2015
-------------------------------------------------------------------------------------------------------------------
                                    Copyright 2015 Cadence Design Systems,
Inc.

WARNING (LBRCXM-624): Warning [input]: Line 6: 'well' statement is ignored in ICT file line.

WARNING (LBRCXM-624): Warning [input]: Line 7: 'well' statement is ignored in ICT file line.

INFO (LBRCXM-630): Starting extraction: Mon Mar 11 13:35:27 2019


ERROR (AGDPRP-31040): output_setup -net_name_space "SCHEMATIC" is not supported with extract-only data. Specify output_setup -net_name_space "LAYOUT" instead.

INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
 agdsPrep -V -rundir /home/marben/query_output/query_output -outdir /home/marben/query_output/query_output/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile

Forking: agdsPrep -V -rundir /home/marben/query_output/query_output -outdir /home/marben/query_output/query_output/r1 -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/r1/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile
ERROR (LBRCXM-633): Bad return status from RCX script generator. Status 256

INFO (LBRCXM-709): *****  Quantus QRC terminated abnormally  *****

  • in reply to Marben

    Hi Marben

    Thanks for the update. Here are my comments:

    a. Now we know that your "MASK SVDB ..." cmd in the Calibre LVS deck was overwritten by the cmd which was generated by the Calibre LVS form. Thanks for solving the problem. The query output looks correct now

    b. In "Run Details" tab in Quantus form, the run name should be "Design" and not "r1". Would you please change it and re-run extraction?


    Best regards
    Quek

  • in reply to Quek

    Hi Quek,

    I replaced r1 to Design, but same error exist.

    Fullscreen qrc.Design.log Download 
    
  Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
15.1.4-s005 Fri Nov 20 15:19:16 PST 2015
-------------------------------------------------------------------------------------------------------------------
                                    Copyright 2015 Cadence Design Systems,
Inc.

WARNING (LBRCXM-624): Warning [input]: Line 6: 'well' statement is ignored in ICT file line.

WARNING (LBRCXM-624): Warning [input]: Line 7: 'well' statement is ignored in ICT file line.

INFO (LBRCXM-630): Starting extraction: Mon Mar 11 15:27:16 2019


ERROR (AGDPRP-31040): output_setup -net_name_space "SCHEMATIC" is not supported with extract-only data. Specify output_setup -net_name_space "LAYOUT" instead.

INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
 agdsPrep -V -rundir /home/marben/query_output/query_output -outdir /home/marben/query_output/query_output/Design -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/Design/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile

Forking: agdsPrep -V -rundir /home/marben/query_output/query_output -outdir /home/marben/query_output/query_output/Design -sch -e /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/layerSetupFile:r1.alm,r1.ilf -pl r1.ports -mcell /home/marben/query_output/query_output/Design/r1.hcl -l /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed/lvsfile -i r1.ixf,r1.lph,r1.sph:r1.gdx -n r1.nxf,r1.stl:r1.gnx -s r1_pin_xy.spi:r1.xcn,hccidtmfile
ERROR (LBRCXM-633): Bad return status from RCX script generator. Status 256

INFO (LBRCXM-709): *****  Quantus QRC terminated abnormally  *****

    Please help.

    Best regards,

    Marben

  • in reply to Marben

    Hi Marben

    I think the error has already changed.Previously we had this error:

    >>> ERROR (AGDPRP-31003): can't open /home/marben/query_output/query_output/r1_pin_xy.spi
    This has already been resolved by setting "Run Name" as "Design"

    Now we have this error:
    >>> ERROR (AGDPRP-31040): output_setup -net_name_space "SCHEMATIC" is not supported with extract-only data. Specify output_setup -net_name_space "LAYOUT" instead.

    This is really quite strange. Although we can resolve the error by using "Layout" namespace in "Netlisting" tab, it should not be necessary. It seems that you had executed Calibre using "calibre -lvs" and not "calibre -ext" and hence the data should not be "extract-only".

    Would you please file a case to Cadence support centre so that they can have a look at it?

    Thanks
    Quek

  • in reply to Quek

    Hi Quek,

    Thank you for your help and reply.

    I will file a case to Cadence support.

    Best regards,

    Marben

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.