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ERROR (SFE-841): "input.scs" 19

Shobhitkareer

Hi,

I'm trying to implement an example from Andrew written in verilog A using ADEXL spectre, I have written the following code to simulate Chi distribution in monte carlo


module FET_MC1_Chi(Drain,Gate,Source,Sub);

parameter real mean =19;
parameter integer seed= 1234;
parameter real rpoisson_mis=$rdist_poisson(seed,mean,"instance");
parameter real rpoisson_proc=$rdist_poisson(seed,mean,"global");

localparam real a_eff = a+ rpoisson_mis + rpoisson_proc;
localparam real b_eff = b ;

endmodule

and my statistical block is the following

parameters mean=0.0;

statistics {

mismatch {

vary mean dist=gauss std=1.6
}
process {


vary mean dist=gauss std=0.1
}

}

The error observed are

ERROR (SFE-841): "input.scs" 18: Unexpected character `$' in netlist.
ERROR (SFE-841): "input.scs" 19: Unexpected character `$' in netlist.

Additionally it makes seedmeaninstance and seedmeanglobal as two variables..

I have also written ahdl_include FET_MC1_Chi.va to mitigate the problem. However, to which I got the error

 Can not open input file `FET_MC1_Chi.va'. No such file or directory. Ensure that the file exists and the path to the file is correct. Otherwise, use the -I<path> command-line option to specify the path to the file.

To solve this I tried implementing setenv CDS_VLOGA_INCLUDE /.automount/infofa/h/users/skare0/FET/model5

Please give me your valuable suggestion to what I'm doing and how can I connect it. I'm using IC617

Regards

Shobhit

  • Andrew Beckett

    The first error is because you tried to include the VerilogA model directly in spectre, whereas it has to be included via an ahdl_include. 

    If the VerilogA file is in the same directory as the file containing the ahdl_include, then it should work. The $CDS_VLOGA_INCLUDE is for the path for `include statements inside the VerilogA, not for finding the file for ahdl_include. That is found using spectre's usual include path (in ADE, it's Setup->Simulation Files->Include Path, or on command line for spectre it would be via the -I/path/to/where/veriloga/is/found )

    Andrew.

  • Shobhitkareer
    in reply to Andrew Beckett

    Hi Andrew,

    Thank you for your reply. But I had tried that but I still got

    ERROR (SFE-841): "input.scs" 18: Unexpected character `$' in netlist.
    ERROR (SFE-841): "input.scs" 19: Unexpected character `$' in netlist.

    And also I keep on getting warning that my variable seedmeaninstance and  seedmeanglobal is not set which I defined as 

    parameter integer seed= 1234;
    parameter real rpoisson_mis=$rdist_poisson(seed,mean,"instance");
    parameter real rpoisson_proc=$rdist_poisson(seed,mean,"global");

    And also I thought my environment is not verilogA which I changed as cmos_sch cmos.sch schematic veriloga spectre

    Thank you in advance

    Regards

    Shobhit

  • Andrew Beckett
    in reply to Shobhitkareer

    Hi Shobhit,

    You must be doing something very wrong here, because what you're saying makes no sense at all. The best way of handling this would be through customer support because I suspect there's a whole load of things you're doing incorrectly. However, assuming that you're at at university, let me attempt to get to the bottom of this by asking some questions:

    1. How are you running your simulations? Is it using ADE L or via some other ADE tool? Which version (that's probably not critical to know here, but may come in handy later)?
    2. Can you please share a screenshot of Setup->Model Libraries?
    3. Please also share a screenshot of Setup->Simulation Files
    4. I assume with the "my environment is not verilogA which I changed..." you were talking about the view list on Setup->Environment in ADE. That would be irrelevant if you're doing the ahdl_include from a file rather than having the veriloga view in a Virtuoso library
    5. Can you show a screenshot of the ADE window? I can't see why it would come up with variables called seedmeaninstance or seedmeanglobal.
    6. Please also show the input.scs - I can't see how it would have $ in the input.scs - that seems very strange

    There may be others - but your setup sounds totally messed up - so I'm trying to avoid all assumptions that anything is correct and understand what you've done since you've not really provided a great deal of information.

    Regards,

    Andrew.

  • Shobhitkareer
    in reply to Andrew Beckett

    Hi Andrew,

    1. Its using ADE L for IC 6.1.7

    2.

    3. 

    5.

    6. I have not included input.scs, only a statistical block. But when I run the monte carlo, I get ERROR (ADEXL-5069): Monte Carlo run stopped because no statistical data generated for the test: shobhit:ncnfet:1

    Thank you in advance

    Regards

    Shobhit

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