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functional mismatch of pre and post layout simulation results

abhi21

In cadence virtuoso, with scl pdk 180 nm technology, the schematic is correct  and is showing the correct pre layout simulation result using ADE L. After designing the Layout, there is no DRC error found and LVS result is also correct but the post layout simulation result I am getting is wrong ... as in pre layout simulation, the output voltage is coming out to be 1.0024V and in post layout simulation, for the same set of inputs, output is coming out to be 1.63V. Please give some solution.

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  • Andrew Beckett

    Do you really expect anyone to be able to give you a solution from the info you've provided in the question above? Please read the Guidelines for the Custom IC Design Forum. Put yourself in the shoes of the person trying to answer - have you supplied enough information that means there is a hope of being able to answer?

    Kind Regards,

    Andrew.

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  • Andrew Beckett

    Do you really expect anyone to be able to give you a solution from the info you've provided in the question above? Please read the Guidelines for the Custom IC Design Forum. Put yourself in the shoes of the person trying to answer - have you supplied enough information that means there is a hope of being able to answer?

    Kind Regards,

    Andrew.

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