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Plotting VerilogA String Variables

Tjaart

I have written a VerilogA testbench that runs a few automated tests using IC6.1.7 and SPECTRE171.

I thought it would be useful to plot the current test phase as a string on the waveform as this could help with analog debugging along the x-axis (time).

I might have managed to update a string variable at the start of every phase, but now it seems that I cannot access the variable in the VIVA results browser. I have also changed the output format to SST2 and tried using Simvision but this also did not work. I have made sure that "saveahdlvars" is set, and I can currently access and plot all the real and integer VerilogA variables.

I have done something similar inside a SystemVerilog bench through a Mixed-Mode simulation, but right now I want to avoid expanding my bench this far.

Is there a way for me to plot this variable on a waveform viewer?

  • Andrew Beckett

    Could you provide your model (or a simplified but working version of your model) so that we don't have to try and create something that (by guesswork) does what you're doing?

    Thanks,

    Andrew.

  • Tjaart
    in reply to Andrew Beckett

    `include "constants.vams"
    `include "disciplines.vams"

    `define OFF_CURRENT 1p
    `define ON_CURRENT 10p

    module dynamic_chk;

    parameter real refresh_rate = 10n;
    parameter string pin_name_sig1 = "path.to.sig1";
    parameter string pin_name_sig2 = "path.to.sig2";

    parameter real tr = 1n;
    parameter real tf = 1n;

    integer start_count, counter;
    string message;

    string msg_check_1 = "Check 1 has started";
    string msg_check_2 = "Check 2 has started";

    real I_node1, I_node2;

    analog function integer check1;
    input count;
    inout start_count;
    inout sig1, sig2;

    integer count, start_count, stop_count;
    integer rel_count;
    real run_count = 60u/refresh_rate;
    real sig1, sig2;

    begin
    stop_count = run_count + start_count;

    if ((count >= start_count) && (count < stop_count)) begin
    rel_count = count - start_count;

    //Add code here:
    if (rel_count == 0)
    sig1 = `OFF_CURRENT;

    if (rel_count > 10u/refresh_rate)
    sig2 = `ON_CURRENT;

    if (rel_count > 20u/refresh_rate)
    sig1 = `OFF_CURRENT;

    check1 = 1;
    end

    check1 = 0;

    start_count = stop_count;
    end
    endfunction

    analog function check2;
    input count;
    inout start_count;
    inout sig1, sig2;

    integer count, start_count, stop_count;
    integer rel_count;
    real run_count = 40u/refresh_rate;
    real sig1, sig2;

    begin
    stop_count = run_count + start_count;

    if ((count >= start_count) && (count < stop_count)) begin
    rel_count = count - start_count;

    //Add code here:

    check2 = 1;
    end

    check2 = 0;

    start_count = stop_count;
    end
    endfunction

    analog begin

    @(timer(0, refresh_rate, 10n)) begin
    start_count = 100;

    if (check2(counter, start_count, I_node1, I_node2)) message = msg_check_2;
    if (check1(counter, start_count, I_node1, I_node2)) message = msg_check_1;

    if (counter == start_count)
    $finish_current_analysis(2);
    counter = counter + 1;
    end

    I(pin_name_sig1) <+ transition(I_node1, 0, tr, tf);
    I(pin_name_sig2) <+ transition(I_node2, 0, tr, tf);

    end

    endmodule

  • Tjaart
    in reply to Andrew Beckett

    In the code that I have posted, I want to plot the variable "message" onto a waveform viewer, in order to visibly align any analog signals that I am also plotting.

  • Andrew Beckett
    in reply to Tjaart

    This doesn't seem to be possible from my experiments. I didn't find a request to support saving string variables from VerilogA (might be slightly tricky, because the database format probably doesn't support this right now anyway). 

    You should contact customer support to request this as an enhancement.

    Kind Regards,

    Andrew.

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