Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 13309
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

how to set netSet to connect power of sub-cell to top level cell to pass lvs

Nhumai

Hi All,

I have a top level schematic name cell_top. In cell_top I have 2 instance name cell_A and cell_B. Cell_A and cell_B are generated by innovus play and route flow which don't have any power pin. Inside of cell_A and cell_B the power net name is vdd! and vss! which inherit from vendor lib. On the cell_top, cell_A power  connect to vddl_lvt and vssd_lvt and cell_B connect to vddl_mvt and vssd_mvt. 

Layout is connected  properly but schematic can't since there is no power pin to cell_A and cell_B. I heard that we can connect it using netSet but I don't know how to to that . Can someone please help 

thanks 

Nhumai 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.