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Layout versus Schematic design issue

NorNand

Hi

I am going to start with my layout design. I have a big amplifier with a biasing circuit. I remember from my past work the problem when I finish with my layout and running the layout versus schematic then if I have an error it will be hard to identify and or more difficult to correct it. The difficulty will rise exponentially if the correction needs to be redesigned for some parts in the middle of the layout. 

Is there an option in cadence layout tools where I can run the LVS at any level of my layout design by excluding the remaining of the circuit. Just as an example I would select to layout only the differential pair transistors then I run the LVS, if LVS is ok then I continue to layout the next transistors and so on until I finish with the circuit. Such an option will be also useful to simulate the circuit at each added part of the layout.

I have tried similar kind of trick by dividing the circuit in many parts and put every part in symbol and layout it individually, after then I connect the whole symbols to build back my circuit, but this method is mostly like designing digital system from different cells. However, in digital cells are mostly unique cells where one can connect them easily, not like the analog circuit cells.


Thanks

Parents
  • Andrew Beckett

    This isn't really possible with LVS (well, there is a way, but I doubt it would help achieve what you want). It's possible to ignore devices in LVS by putting a boolean property on the instance, lvsIgnore=t. However, since you'd then have a number of floating devices in the layout you may actually find it harder to achieve LVS correctness. Plus re-simulating won't really be possible because all the ignored components won't be in the circuit.

    A better approach would be to use Virtuoso Layout Suite XL to perform your layout. Since this is connectivity driven, the chances of LVS-correctness at the end are much higher - it will show you the missing or incorrect connectivity as you create the layout. You can then use the Layout EAD (Electrically Aware Design) tool (if you have it) to perform parasitic extraction on the partial layout, and using the layout-dependent-effects capability, simulate the partially laid out circuit. Essentially this would take the device parameters from the devices  you have laid out, and the parasitics from the nets laid out, but include any missing devices from the schematic in any simulation.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    This isn't really possible with LVS (well, there is a way, but I doubt it would help achieve what you want). It's possible to ignore devices in LVS by putting a boolean property on the instance, lvsIgnore=t. However, since you'd then have a number of floating devices in the layout you may actually find it harder to achieve LVS correctness. Plus re-simulating won't really be possible because all the ignored components won't be in the circuit.

    A better approach would be to use Virtuoso Layout Suite XL to perform your layout. Since this is connectivity driven, the chances of LVS-correctness at the end are much higher - it will show you the missing or incorrect connectivity as you create the layout. You can then use the Layout EAD (Electrically Aware Design) tool (if you have it) to perform parasitic extraction on the partial layout, and using the layout-dependent-effects capability, simulate the partially laid out circuit. Essentially this would take the device parameters from the devices  you have laid out, and the parasitics from the nets laid out, but include any missing devices from the schematic in any simulation.

    Regards,

    Andrew.

Children
  • NorNand
    in reply to Andrew Beckett

    Hello Andrew

    Thanks for your nice explanation details

    I would go for your suggested "better approach" by running the  Layout Suite XL ,  

    From the practical work, I see this approach is perfect if the transistors from the schematic is picked as it to the layout. If I make the number of gates in the layout different (for the purpose of matching ) and or if  I subdivide the transistors between other transistors (like matching differential or current mirrors transistors, e.g, ABAB) then I see that connectivity guidance of the Layout Suite XL is not working well.

    Usually, I design in my schematic all the transistors with a number of gates equal to one, but in the layout, I change it according to the complexity of matching that I decide it at the time of layout.

     I am not sure (or didn't noticed) if I have the EAD tool or not because I usually work with Assura DRC, LVS and QRC. It seems from your explanation that EAD tool is a specialist tool for partial layout design.  

     I will check about the EAD tool  later and I will inform you  

     Thanks   

  • NorNand
    in reply to NorNand

    Hello Andrew,

    I checked that I don't have EAD tool in our Cadence. 

    I can confirm to you now that  connectivity driven from Layout XL is not functioning if I split my transistors or merge the common parts (drain and source),  

    Thanks 

  • Andrew Beckett
    in reply to NorNand

    You may be able to use Connectivity->Generate->Folded Devices which allows you to rearrange the ratio of the devices. The help button on the form for that command will take you to the relevant section of the documentation - or perhaps you could talk it through with customer support to make sure we fully understand what you're trying to do. I suspect it is possible given the right metholodogy.

    Regards,

    Andrew.

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