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  3. VerilogA, one or the other parameter implementation

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VerilogA, one or the other parameter implementation

Emiel
Emiel over 6 years ago

In for instance the port cell in analogLib you can enter for a certain signal either the Amplitude (Vpk) or the Amplitude (dBm). When one of them gets filled in, the other field blanks out.

Is it possible to achieve the same using verilogA? If so how would this be implemented?

Regards,

Emiel

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  • Andrew Beckett
    Andrew Beckett over 6 years ago

    Hi Emiel,

    This is not something that would be done with VerilogA - it's CDF (Component Description Format) that handles this kind of thing. You would go to Tools->CDF->Edit in the CIW, pick "Base" as the type and pick the cell you're creating, and for the two parameters (I'm assuming they are called vpk and dbm) you'd set the editable condition to:

    vpk:    blankstrp(cdfgData->dbm->value)

    dbm:   blankstrp(cdfgData->vpk->value)

    In other words, each field is editable if the other field is a blank string. You can also change the prompts to something more readable than the parameter name for each parameter in the CDF.

    Regards,

    Andrew.

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  • Emiel
    Emiel over 6 years ago in reply to Andrew Beckett

    Hi Andrew,

    Thank you, blanking out the field with your mentioned display condition in the CDF editor works fine.

    I'm however not sure how to determine in the code which parameter is filled out (and should be used for the calculation) and which parameter is blanked out (and should not be used for the calculation).

    I'm initializing them as:

    parameter real vpk = 0;

    parameter real dbm = 0;

    Something like this is wanted (pseudo:)

    if vpk is filled in

         z = vpk

    else if dbm is filled in

         z = 2*dbm

    end

    Testing if a parameter is filled in by testing if it is unequal to 0 is not very neat either. Since the filled in value can also be 0 and the blanked out value also evaluates to 0.

    Regards,

    Emiel

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to Emiel

    Hi Emiel,

    A couple of approaches that you might use. The first is just to have a default value of the parameter that you wouldn't use normally and check for that in the model - if the value in the CDF is blank, it's not passed to the component and the VerilogA would see its default value - and the model could then check if the parameter was at this default to determine if it was passed in or not.

    The second is to add another parameter to the model - e.g.

    parameter integer vpk_supplied=0;

    Then in the CDF you would have this vpk_supplied parameter with a display condition of nil so that it doesn't show up (the CDF default would be 0 to match the model). On the vpk parameter have a callback with this expression:

    cdfgData->vpk_supplied->value=if(blankstrp(cdfgData->vpk->value) then "0" else "1")

    Then you'll know if vpk_supplied==1 then the vpk has been filled in, otherwise dbm (or something like that).

    Regards,

    Andrew.

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  • Emiel
    Emiel over 6 years ago in reply to Andrew Beckett

    Works great, thank you.

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