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Virtuoso 6.1.8 plotted expressions in VIVA do not fit to evaluated expressions in assembler

Michael H

Hello,

I encountered the following problem using cadence virtuoso IC6.1.8 ISR3 with SPECTRE 18.1 ISR6.

I did an stb analysis with a global variable sweep ("temperature" and "L"). Furthermore, I created several expressions for dc gain, phase margin and so on. The expressions are evaluated fine inside assembler. If I now right click on one evaluated expression for the phase margin and select "Plot All" I get the depicted window in VIVA - but the values do not match the expression results in assembler (They are somehow mirrored regarding the sweep variable "L").

Nevertheless, if I mark multiple phase margin results in assembler and click on "Plot" I get the correct results. I also attached a picture from that at the end.

This behaviour does not happen always, but it occurred several times to me.

Regards,

Michael

 

Wrong plotting

correct plotting

Parents
  • Andrew Beckett

    Michael,

    Not sure if this is a known issue or not (I’m travelling so can’t check) but I would recommend reporting this to customer support.  If it’s not known then we can investigate - if it is known at least we can tell you when a fix will be available (hopefully)

    Regards,

    Andrew

  • Michael H
    in reply to Andrew Beckett

    Hi Andrew,

    thanks for your quick response, I submitted a case.

    Regards,

    Michael

Reply
  • Michael H
    in reply to Andrew Beckett

    Hi Andrew,

    thanks for your quick response, I submitted a case.

    Regards,

    Michael

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