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Inconsistent phase noise results of divide-by-2 phase using different PNOISE method

Cod Liang

Hi,

I've been simulating phase noise of a divide-by-2 circuitry with PSS & PNOISE.

The schematic is a simple master-slave based DFF drived by two inverters.

Also the input source is sinusoidal with phase noise profile extracted from crystal oscillator's simulation result. 

The phase noise of interest is CK52M_1 & CK26M, and the PSS & PNOISE settings are as below:

PSS

PNOISE 52M

PNOISE 26M

PNOISE 52M Sampled(Jitter)

PNOISE 26M Sampled(Jitter)


Because I cared only about the timing(phase) modulation of the clocking signal, thus for timeavg method I just plot PM noise.

The overall results are shown below:

According to the simulation, there are some phenomenons that I cannot explain:

A. For Timeavg+PM method

1. 26-MHz phase noise is about 6dB better than 52-MHz one at very low frequencies(100~1kHz).

    Both noises in this region is dominated by XO's phase noise.

2. However, when offset frequencies go further(1k~1MHz), the result is reversed and the noise gap is larger than 6dB.

    And 26-MHz noise in this region is dominated by 1st inverter's flicker noise. (90%)

    But for 52-MHz one, flicker only contributes about 37%.

3. For frequencies >1MHz, 26-MHz noise crosses behind 52-MHz one again and exhibits about 3dB better.

    Both noises are dominated by 1st inverter's thermal noise.

B. For Sampled Jitter method 

1. Both 26M and 52M show roughly same Jee.

    freq < 1kHz, both are dominated by XO's noise.

    1k < freq < 1MHz, both are dominated by 1st inverter's flicker noise (90%).

    freq > 1MHz, both are dominated by 1st inverter's thermal noise.

2. If we plot Jee in "Edge Phase Noise" form (available in latest version of Virtuoso), both 26M and 52M noise are almost identical.

    Since "Edge Phase Noise" is converted by Jee with respect to fundamental carrier freq. (26MHz), the intrinsic 52-MHz phase noise is supposed to be 6dB worse than 26-Mhz one.

Here is the problem that confuses me a lot:

Why does the noise performance of Timeavg+PM and Sampled Jitter give me quite different results?

For divided 26-MHz case, both methods at least show same noise level at freq. < 100kHz. 

But for undivided 52-MHz clock, Timeavg+PM give me > 10dB improvement than Sampled Jitter one.

Which way should I trust?

Or if it is to implemented in frequency synthesizer, which method gives me much more accurate noise estimations?

Truly thanks for help.

 

 

Parents

  • Sampled Jitter is the correct method here, because your circuits are edge-sensitive, so that only the jitter of these edges matters. This is also confirmed by the consistent results that you are getting with this method. See also Cadence Solution 20482538.

  • in reply to Frank Wiedmann

    Hi Frank,

    Actually I had read the solution you post before.

    But the reason why I've been questioning these two methods is the silicon measurement told me the results agreed much more with timeavg+PM. I measured the phase noise of a 52-MHz XO fabricated in UMC .18um with E5052B(Signal Source Analyzer). And the phase noise of divided 26-MHz indeed "degraded" from about 1k~1MHz offset frequencies, which is similar to the figure I've post. Based on the real silicon verification, it is quite hard for me to trust that "sampled jitter method is the only way to judge logic circuits noise behavior".

    Regards,

    Liang

  • in reply to Cod Liang

    Hi Liang,

    Measurement equipment usually measures time-average noise, so if you want to compare your simulation results to measurements, this is the correct way. However, if you connect an edge-sensitive device to the output of your circuit, the jitter of these edges (and not the time-average phase noise) is the relevant quantity.

    Best regards,

    Frank

  • in reply to Frank Wiedmann

    Hi Frank,

    Thanks for your reply. I just studied the manual of Signal Source Analyzer and your comments are right. The measurement is based on time-average(or frequency-domain) method. So let's go back to my question. If for such edge-sensitive circuits like frequency synthesizers, what we care about at the output is also edge information, right? If so, if we have to budget noise sources contributing to synthesizers such as crystal oscillators, what I really care about is sampled jitter noise rather than timeavg. noise. Therefore the measured results come from Signal Source Analyzer (or some other measurement equipment that measure in freq. domain) is not the actual case the circuit would "behave", right? Similarly, the output phase noise of synthesizers measured by the same equipment would also give me some "misleading" information of noise performance. In contrast, although sampled jitter could give me "correct" answer, I think it is hard to get correlation between simulation and measurement results. I just wonder how could I precisely estimate noise performance of such logic circuits if there is a gap between these two methods.

    Best regards,

    Liang

  • in reply to Cod Liang

    Hi Liang,

    If you connect the output of your circuit to an edge-sensitive device, then you should care about the jitter of these edges. You can measure jitter directly with a fast real-time digital oscilloscope. Alternatively, if you have a good simulation model of your circuit, you can compare the measured time-average noise with the simulated time-average noise. If they match well, it is quite likely (but not absolutely certain due to the lack of a direct correlation between jitter and time-average noise) that the simulated jitter of your circuit will also match the actual jitter pretty well.

    Best regards,

    Frank

Reply
  • in reply to Cod Liang

    Hi Liang,

    If you connect the output of your circuit to an edge-sensitive device, then you should care about the jitter of these edges. You can measure jitter directly with a fast real-time digital oscilloscope. Alternatively, if you have a good simulation model of your circuit, you can compare the measured time-average noise with the simulated time-average noise. If they match well, it is quite likely (but not absolutely certain due to the lack of a direct correlation between jitter and time-average noise) that the simulated jitter of your circuit will also match the actual jitter pretty well.

    Best regards,

    Frank

Children
  • in reply to Frank Wiedmann

    Hi Frank,

    Thanks for your useful information. 

    Besides, do you have any comments on another questions, i.e., frequency divider's noise performance gap between sampled jitter and time-average?

    Best regards,

    Liang

  • in reply to Cod Liang

    Hi Liang,

    For digital circuits, time-average noise often includes large time intervals with very low noise when the output is clipped either to the supply voltage or to ground. These time intervals have a significant influence on the time-average noise, but are of course completely irrelevant for the jitter of the signal edges.

    Best regards,

    Frank

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