veriloga integer input to 32-bit address output has a strnage error/how to debug/where to find the latest veriloga reference documents?

A slightly unusual way of coding it - you have one or two voltage contribution statements for each bus bit - what will happen is that if both are enabled, it would get the sum of the two.

It works absolutely fine for me in SPECTRE18.1 ISR8 (you’re using iSR3) - although it’s a bit surprising you’d be getting a segmentation fault (I can’t easily check the older version as I’m travelling).

The documentation for VerilogA is in the SPECTRE stream - if you do `spectre_root`/bin/cdnshelp you can access it that way, or look in the doc directory under the location reported by spectre_root (in a terminal) - it’s veriaref/veriaref.pdf

The $debug and $strobe in your code works absolutely fine (of course, once uncommented). I assume the segmentation fault you’re getting is before it even gets that far. I don’t see why it should be crashing - so I’d advise checking a newer hot fix in case it was a temporary issue that’s now been resolved.

By the way, there is a component on support.cadence.com called “busset” (or rather “bussetp” - search for either and I think it will find the article) which is something I put together a few years ago which is a parameterised component with a variable width bus. That allows you to provide a parameter which is the decimal value of the bus. The maximum bus width is (I think) 31 though in that case (so you could just place two instances with 16 bits each if you want 32. That doesn’t use VerilogA.

Regards,

Andrew.

I am able to find the veriaref files, thank you. 

Hi Andrew:

Thanks for the support. The reason I am back is because the veriloga code failed for some other reason and I am not able to figure out how to properly load your skill code bussetp.il.

I load it in CIW and it returns with the below error.

=======start error report=============

load("~/Downloads/bussetp.il")
*Error* Couldn't open library "training"
*Error* load: error while loading file - "~/Downloads/bussetp.il" at line 284

=========end of error report==================

For the veriloga code, I have simplified my code to the code below but I still get error now, it works yesterday, weired.

`include "constants.vams"

`include "disciplines.vams"

module integer2thermocodeOut(vdda,gnda,OutAddress);

parameter integer BusWidth=32;

parameter integer BusOn=8;
input vdda, gnda;
output [31:0] OutAddress;
electrical [31:0] OutAddress;
electrical vdda, gnda;

genvar i;

analog begin

if (BusOn) begin

for(i=0;i<BusOn;i=i+1) begin

V(OutAddress[i]) <+ 1.0*V(vdda);
end
end
end

endmodule

=======start error report=============

Error found by spectre during hierarchy flattening.
ERROR (SFE-100): "input.scs" 6403: `I101': An instance of `integer2thermocodeOut_BusOn_12' can have at most 0 terminals (but has 34). Clean up the directory and recompile or use command '-va,forcecompile' to recompile. If still fail, contact developer for help.

========end of error report==========

I am using IC6.1.7-64b.500.23

The busset code will need modifying to specify the library you wish to create the component in. From memory the code specifies it as a library called "training" but you can change the code to be whatever you want. That's why it's failing. Note however that you cannot create a bus wider than 31 bits though using this component because uses integer arithmetic and it's signed 32-bit integer.

The VerilogA code should work OK - I suspect something has got messed up with your ADE simulation directory. You could try doing what it suggests - go to Setup->Environment and in the User Command line Option field enter:

-va,forcecompile

This will force the VerilogA to be recompiled. I'm not sure why it's failing without that (may depend on the Spectre version you're using though, which you didn't mention).

Regards,

Andrew.

Hi, Andrew:

I am using an alternative called bmslib→busset8. It's already in the library bmslib.

Besides that, the veriloga coded busset I use before will results in Cadence APS simulator not-convergence. The issue can be confirmed in ic6.1.8-64b.500.16. Since I have a workaround here and doesn't have time to debug this, I just left this info here for reference.

Besides that, it seems the Cadence community webpage is not compatible with chrome browser, opening this page in chrome will results in continuous refreshing, I really cannot read anything in Chrome browser.

monglebest