Using custom VHDL library in cadence VHDL-AMS

There's an error in this code (around line 849 - there's a missing return in a function), but after correcting that I just used:

xmvhdl -work worklib random.vhd

to compile in the package. I'd suggest looking at this Rapid Adoption Kit:

IC6.1.8: Precompiled libraries and Automatic Package handling by UNL for AMS simulations from Virtuoso ® ADE

Andrew.

Thanks a lot Andrew.

But, I think xmvhdl  is a xceliummain command.

I have been using incisive.

I loaded xceliummain . But now, I am seeing  error:- ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /../cadence/xceliummain/19.03.007/tools/inca/files/STD.

Though, I am seeing standard folder in /../cadence/xceliummain/19.03.007/tools/inca/files/STD.

Can you tell me why it is coming up and how to fix this. Also, what is the difference between incisive and xcelium.

My guess is that the configure step wasn't done when installing the XCELIUM release. This is vital for VHDL libraries.

The article VHDL parser error *F,DLUNNE: Can't find STANDARD at <path>/tools/inca/files/STD helps on this - the simplest way would be (as the owner of the XCELIUM release):

cd <pathToXceliumRelease>
./installData/XCELIUM1903_lnx86/batch_configure.sh

where XCELIUM1903_lnx86 is whatever is the relevant path for the version you're using (hopefully this is right).

XCELIUM is simply a newer generation of the digital functional verification tools. Older versions were called INCISIVE. The last INCISIVE version was the 15.20 release, and there have been several XCELIUM releases since then. If using INCISIVE, you'd need to use "ncvhdl" instead of "xmvhdl".

Regards,

Andrew

Thanks a lot Andrew.

I added the following lines in cds.lib:-

softinclude /../xceliummain/19.03.007/tools.lnx86/inca/files/IEEE_vhdlams/cds.lib
UNDEFINE ieee
DEFINE ieee /../xceliummain/19.03.007/tools.lnx86/inca/files/IEEE_vhdlams/IEEE

I compiled with the xrun command (following the document) as below:- 

xrun -compile -makelib /proj/../random random.vhd -endlib.

It successfully compiled without errors. In the folder /proj/../random, I find the two files:--> cdsinfo.tag    xm.lnx8664.067.pak. 

I included the library in cds.lib as DEFINE random  /proj/../random. The random library comes up in Library Manager.

But, when I ran a TB in AMS simulator with ADE-L with one cell using this random package as :- 

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.electrical_systems.all;
use ieee.math_real.all;
library random;
use random.rng.all;

........

........

I got the following errors as below:-

/proj/../dco/beh/vhdl.vhms:
library random;
|
xmvhdl_p: *E,LIBNOM (/proj/../dco/beh/vhdl.vhms,5|13): logical library name must be mapped to design library [11.2].
use random.rng.all;
|
xmvhdl_p: *E,IDENTU (/proj/../dco/beh/vhdl.vhms,6|9): identifier (RANDOM) is not declared [10.3].
architecture beh of dco is
|
xmvhdl_p: *E,ENNOFN (/proj/../dco/beh/vhdl.vhms,17|22): Intermediate file for entity 'DCO' could not be loaded, entity may require re-analysis.
errors: 3, warnings: 0

Can you please tell what is the issue here even after successful compilation. How to fix it ?

Kind Regards,

Also,

I followed the steps given in The article VHDL parser error *F,DLUNNE: Can't find STANDARD at <path>/tools/inca/files/STD.

But, when I compiled (check and save)  the dco entity, I got the following error

DEFINE XMSIMRC ( ./xmsimrc, ~/.xmsimrc )
|
xmvhdl: *F,DLCSYN (../cadence/installs/XCELIUM1903/tools.lnx86/inca/files/hdl.var,4): cds.lib Syntax error 'DEFINE XMSIMRC ( ./xmsimrc, ~/.xmsimrc )'.

Kind Regards,

If i comment DEFINE XMSIMRC ( ./xmsimrc, ~/.xmsimrc ). The following error comes up.

DEFINE VHDL_SUFFIX ( .vhd, .vhdl )
|
xmvhdl: *F,DLCSYN (../cadence/installs/XCELIUM1903/tools.lnx86/inca/files/hdlvhdl.var,5): cds.lib Syntax error 'DEFINE VHDL_SUFFIX ( .vhd, .vhdl )'.

If I comment DEFINE VHDL_SUFFIX ( .vhd, .vhdl ). The following error comes up.

DEFINE VERILOG_SUFFIX ( .v )
|
xmvhdl: *F,DLCSYN (../cadence/installs/XCELIUM1903/tools.lnx86/inca/files/hdlvlog.var,5): cds.lib Syntax error ' DEFINE VERILOG_SUFFIX ( .v )'.

If I comment DEFINE VERILOG_SUFFIX ( .v ).  The following error comes up in CIW

(TE-4223): Extracting cellview 'test dco entity' ...
Updated cellview ... (test dco entity)
Updated cellview ... (test dco beh)
"xmvhdl: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.\n"
"xmvhdl_p: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.\n"
"xmvhdl_cg: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.\n"
(TE-4308): Extract completed for cellview 'VERILOG_VHDL_AMS bpd entity'

If i comment DEFINE XMSIMRC ( ./xmsimrc, ~/.xmsimrc ). The following error comes up.

DEFINE VHDL_SUFFIX ( .vhd, .vhdl )
|
xmvhdl: *F,DLCSYN (../cadence/installs/XCELIUM1903/tools.lnx86/inca/files/hdlvhdl.var,5): cds.lib Syntax error 'DEFINE VHDL_SUFFIX ( .vhd, .vhdl )'.

If I comment DEFINE VHDL_SUFFIX ( .vhd, .vhdl ). The following error comes up.

DEFINE VERILOG_SUFFIX ( .v )
|
xmvhdl: *F,DLCSYN (../cadence/installs/XCELIUM1903/tools.lnx86/inca/files/hdlvlog.var,5): cds.lib Syntax error ' DEFINE VERILOG_SUFFIX ( .v )'.

If I comment DEFINE VERILOG_SUFFIX ( .v ).  The following error comes up in CIW

(TE-4223): Extracting cellview 'test dco entity' ...
Updated cellview ... (test dco entity)
Updated cellview ... (test dco beh)
"xmvhdl: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.\n"
"xmvhdl_p: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.\n"
"xmvhdl_cg: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.\n"
(TE-4308): Extract completed for cellview 'VERILOG_VHDL_AMS bpd entity'

I don't get any of these errors about the syntax errors. It sounds as if you're including the hdl.var (e.g. <INSTDIR>/tools.lnx86/inca/files/hdl.var) in your cds.lib rather than hdl.var - that's the only way I can imagine you get these (I could get those errors by doing that).

As for the issue with not finding random in the AMS simulation, I'm not sure without seeing the real example. Maybe you will need to specify random as a reference library (Simulation->Options->AMS then Main tab, and scroll down to the "LIBRARY COMPILATION OPTIONS" and click on the "Pre-compiled libraries (-reflib) settings".

Otherwise it will try to find the source and recompile it again - I think you'll need to use it as a reflib in this case.

You'd probably be best creating a case with customer support so that an AE can look at this with you via a screen-sharing session.

Regards,

Andrew.

Dear Andrew,

Thanks a lot.

It is now finding random. I followed your second option:- "Maybe you will need to specify random as a reference library (Simulation->Options->AMS then Main tab, and scroll down to the "LIBRARY COMPILATION OPTIONS" and click on the "Pre-compiled libraries (-reflib) settings". "

But, I am seeing following error

xmelab: *E,DTYPMSM (./netlist.vams,66|23): There is a mismatch in datatype between SV Port : 'top.deltat' (file: ./netlist.vams, line: 52) datatype :  logic and VHDL Port: 'top.I35:deltat' (file: vhdl.vhms,line: 11) datatype : INTEGER.

My ports are defined in the vhdl file for the block bpd as :-

port(
c : in std_logic;
d : in std_logic;
deltat : out integer;
pdout : out std_logic
--d_hystjit_test : out std_logic
);

I wonder why it is taking std_logic port but not taking the integer type port 

Though, I have created the cell view as below:-

And my config view look like and bpd is in beh cellview:- 

Is there any way to ensure that it will take the integer or real type port. How can we make it a vhdlAMS cell view ?

Kind Regards,

My top cell schematic Testbench is as below:-

It has the bpd cell aslo the verilog, verilogAMS cells.

It runs fine in AMS simulation without bpd cell. The bpd cell has beh view in config.