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How to add parameters to VHDL module.

RFStuff

Dear All,

I have some VHDL modules. I need to use them in cadence AMS enviornmnet.

I know to use parameters in Verilog modules.

Are there any ways one can use similar kind of parameter in VHDL module so that one can change the parameters of the cells during simulation.

Kind Regards,

  • Andrew Beckett

    You define parameters in VHDL using GENERIC. I'm sure you can find countless examples on the web - e.g.

    entity comparator is

    generic (level : real := 2.5; -- threshold
    vcc : real := 5.0;
    gnd : real := 0.0);

    -- other definitions in the entity

    end comparator;

    Not entirely sure what you're asking here - if you're asking how to write stuff in VHDL, this isn't really the right forum (probably the Functional Verification or Logic Design forums would be better)

    Andrew.

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