• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Using vcvs as delay elements result in period signal rising...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 15385
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Using vcvs as delay elements result in period signal rising and falling time changing

xianweng
xianweng over 6 years ago

Hi, everyone,

My cadence version is IC6.1.7 and MMSIM version is 13.1. I am using VCVS as delay unit (I know there are some delay component in analogLib like delayline, but there are some other strange phenomena).

The testbench and simulation results are shown in the following figures.  The gain of vcvs is 1 and delay time is 1.1us. The vpulse period is 7ms, pulse width is 800ns as shown in fig2. The result of the first period is right as shown in fig3, but the second period result is wrong as shown in fig4.  The rising and falling time of fig3 are 177ns, which changed significantly. And the fourth period is right. 

Any hint on that?

Best regards,

xianweng

fig1. Testbench

fig2. configuration of vpulse

fig3. The simulation of the first period

fig4. The simulation of the second period

  • Cancel
Parents
  • xianweng
    xianweng over 6 years ago

    Sorry, "The rising and falling time of fig3 are 177ns" should change to  "The rising and falling time of fig4 are 177ns"

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • xianweng
    xianweng over 6 years ago

    Sorry, "The rising and falling time of fig3 are 177ns" should change to  "The rising and falling time of fig4 are 177ns"

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to xianweng

    Please post the input.scs of your circuit (the spectre netlist you are simulating). I'm feeling lazy and don't want to have to reconstruct your circuit from the photos (even screenshots would have been better than photos, but a netlist is better still).

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information