Stats

  • Locked Locked
  • Replies 4
  • Subscribers 125
  • Views 18113
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Bit pattern generator for mixed signal simulation

NorNand

Hello,

I am using Cadence Virtuoso IC6.1.5 64 bit.

In my design I have analog  and digital parallel in-parallel out shift register. I need to fill this register with binary data.

I am using Verilog to generate my digital data bits by designing functional block and put it in my simulation test bench,  then I use to run simulation and set the simulator to 'AMS'.

This configuration is not supporting all the simulations as spectra offers.

The second thing is that I need to write Verilog code every time I need different type of data.

Therefore I would like to ask you please if there is other option provided by cadence to generate pattern of parallel bits (that has configurable times and voltage) which can run under Spectra simulation

Thank you

Best Regards

  • RiadKaced

    Hi @NirNand 

    I would live to help you with this issue, I can write some SKILL code that can automatically generate this binary data in various formats that will handle both Spice (Spectre,Hspice, AFS) and Digital simulators (Xcelium, vcs). All I aneed is a short spec with an example of a binary file and a snpashot of the testbench. Either post it here or send it over to me at riad at feb22 eda dot com. We can do a quick WebEx if that Suits you.

    Riad @feb22eda

  • NorNand
    in reply to RiadKaced

    Dear RiadKaced

    Thank you very much for your reply and your kind wish to help me,

    to make it general easy case to start, I will assume that I want to simulate the BCD to seven segment display decoder. In the following link, you kindly see the signals test which I want to generate

    http://www.ece.mtu.edu/labs/EElabs/EE2304/EE2304_website_2008/week_4_bcd_to_seven_segment.html

    Hope this will be a good example to learn from you. 

    Thank you once again

    I am looking forward to your kind answer 

    Best Regards

  • Andrew Beckett
    in reply to NorNand

    The other thing  you could do is write Verilog code to generate the pattern and sequence you want, and then run a digital simulation on the command line using irun or xrun (could run it in Virtuoso too) and save the output signals in VCD (Verilog Change Dump) format.

    You can then use the Setup->Simulation Files->Vector Files and specify this VCD file together with a information file which specifies the rise/fall times, voltages and so on, and you can use this VCD with Spectre as the simulator. So no need to run everything together - you run one sim to generate the data in a digital or AMS simulation and then consume the resulting VCD in an analog simulator with more analyses.

    Alternatively, you could use the Vector Files and generate the pattern using a script (e.g. in perl, python, Tcl, SKILL - whatever is your favourite language).

    Documentation on the Vector Files and VCD files support in Spectre can be found in the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide manual. Run `spectre_root`/bin/cdnshelp and search for "Vector File" to find it (It's in the UltraSim documentation too).

    Regards,

    Andrew.

  • NorNand
    in reply to Andrew Beckett

    Thank you Mr. Andrew for your useful answer,

    I am aloso in contact with Mr. Kaced about more details of this method

    Best Regards

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.