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  3. How to do back annotation for wire RC extraction from layout...

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How to do back annotation for wire RC extraction from layout to schematic

popoYoHo
popoYoHo over 5 years ago

Hi,

I am testing a simple circuit. There is a difference between post-layout simulation and schematic simulation due to parasitic R and C from wire. I subsititute RC from post-layout extraction into schematic with T model for wire. However, the back annotation on schematic doesn't show same simulation result as I have on post-layout simulation. I am confused about this part. Is my wire model here (L or T model) not correct? or I missed sth?

Could anybody help me with it?

Thanks,

Po

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  • Andrew Beckett
    Andrew Beckett over 5 years ago

    Without knowing what your wire model is here and how you came up with it, I'm not sure anyone can help...

    Presumably your model doesn't match the parasitics from post-layout simulation!

    Regards,

    Andrew.

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  • popoYoHo
    popoYoHo over 5 years ago in reply to Andrew Beckett

    Hi Andrew,

    Thanks for replying me so fast.

    I have got RC parasitic readings from cadence. The RC wire parasitic leads to a discrepancy between my schematic and post-layout simulation results. I use T model for wire and add wire RC using ideal components from anaglib back to my schematic. However, the new schematic simulation does not match my post-layout simulation, which confuses me a lot. I aussum wire model is T or pi. Is that correct? Or are there any other wire RC models for tsmc pdk?

    Thanks

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to popoYoHo

    We do not have a "wire RC model" and nor does any TSMC PDK. I don't know what you mean by "I have got RC parasitic readings from cadence". What is "cadence"? (there is no tool called "cadence"). How are you getting these "RC parasitic readings"?

    If you're using Quantus QRC to do the extraction, it would produce an RC network representing the parasitics on that track and coupling to other tracks. My wild guess is that you're using the visualisation capability that can display a single effective R and C value on the schematic - this is not intended to be used for simulation, but to give you a rough indication of the effective resistance of the net and the total capacitance. For anything other than a trivially simple connection that would give you a pretty inaccurate representation of the actual distributed RC network of the track.

    You would normally simulate using the actual extracted parasitics (e.g. by simulating with an extracted view), but there is support in the tools for selectively picking the parasitics from some nets and keeping the others from the schematic - so you keep your schematic golden but would then allow you to explore the impact of parasitics on specific rather than all nets. But it's unclear what tools you're using, what versions, or what you're actually doing here!

    Kind Regards,

    Andrew.

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