Full chip transistor level simulation convergence problem

Dear All,

      We are working on analog mixed signal chip design, already done AMS simulation, LEC on full logic. We would like to simulate the full chip with both analog and digital circuit in transistor level to double confirm the chip functionality.

      We used ADE in Cadence to run transient simulation but unfortunately the initial condition couldn't be computed successfully. The # of circuit nodes exceed 210k. We set the simulation accuracy to "liberal" already but still not succeed. In what ways we could do to run such transistor level simulation on checking chip functionality. 

      Thank you for your help.

Best Regards,

Chi Fung