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Layout GXL: Binder and master difference

Dear all,

When I am flattening a transistor, adjusting some layers and consequently making a cell, I am getting an following XL status: "master difference, connectivity difference"

I am doing the following:

- RMB -> Flatten -> Preserve: Pins

- RMB -> Make Cell -> Hierarchy: Transparent instance, preserve connectivity and create pins

Am I doing something wrong?

Thanks,

Kind regards,

Nicolas

PS: Using IC6.1.7

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