PNoise simulation of dynamic comparator

Dear experts,

There has been some prior discussion on this topic (https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/16943/noise-analysis-on-dynamic-comparator) and based on the RAK that was recommended in the post I set up a PSS+PNoise testbench for a clocked comparator. In this process, I noticed that the RAK suggests changing the beat period to 2*period where period is the clock period of the comparator clock. The question is, why should the beat period be set to 2*period and not just set based on what auto calculate returns (which happens to be period, given there is only one large signal clk in the design)? Subsequently when I run the PNoise analysis and compute the total integrated noise (as suggested in the RAK), I did notice a difference by up to 20% in the computed IRN (IRN is 20% less when beat period is set to period instead of 2*period). I would appreciate if some one can throw light on the right beat period to be set in this case.

Thanks and regards