Defining device performance with inserting resistance data

I simulated inverter with two verilogA table based models.

But it showed output value higher than Vdd value in some Vgs range.

I don't know what is problem, so I tried to change some parameter of the device.

I tried to insert data of resistance instead of current, but I could not find method to make device with Vds, Vgs, and R.

Is it possible to make transistor with these three parameter Vds, Vgs, and R without data of current?

This is verilogA code of the device.

// VerilogA for STEEP, NHETT, veriloga
`include "constants.vams"`include "disciplines.vams"

module device2(s, g, d);
inout s, g, d;electrical s, g, d;
//real cap_gd_value, cap_gs_value;
//electrical gd_slope, gs_slope;parameter real width = 1;
parameter real current_degradation = 1;parameter real direction = 1;
// 1:strong, -1:weakparameter real mismatch = 0;analog begin
    //cap_gd_value = $table_model( V(g) - V(s), V(d) - V(s), "/net/fet.eecs.umich.edu/z/shared/funt/STEEP/table/cap_gd.tbl", "1C,1C");
    //cap_gs_value = $table_model( V(g) - V(s), V(d) - V(s), "/net/fet.eecs.umich.edu/z/shared/funt/STEEP/table/cap_gs.tbl", "1C,1C");
// V(gd_slope) <+ ddt(V(g) - V(d)) * 1e-9;
// V(gs_slope) <+ ddt(V(g) - V(s)) * 1e-9;
// I(g, d) <+ cap_gd_value*V(gd_slope) * 1e9 * width;
// I(g, s) <+ cap_gs_value*V(gs_slope) * 1e9 * width;
   I(d, s) <+ $table_model (V(d) - V(s), V(g) - V(s) + direction*mismatch, "sample1.dat") * width * current_degradation; 
end
endmodule

Thanks.