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Unbound pins when running Assura LVS in Virtuoso Layout

jyoti kandpal

hello sir, when i draw the layout of the buffer circuit, there is no DRC error but there is one LVS error that occurred which is related to unbound pin.i attached the image of my layout, in this image the highlighted part shows the error.

  • jyoti kandpal

    In my schematic, there are only 4 pins. In LVS an error occurred between the drain of the first inverter to the gate of the second inverter which shows unbound pin error, how I can resolve this issue please suggest some options.

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